How to use the pyrtl.working_block function in pyrtl

}

# for simulation purposes, we can give the spots in memory an initial value
# note that in the actual circuit, the values are initially undefined
# below, we are building the data with which to initialize memory
mem1_init = {addr: 0 for addr in range(8)}
mem2_init = {addr: 0 for addr in range(8)}

# The simulation only recognizes initial values of memories when they are in a
# dictionary composing of memory : mem_values pairs.
memvals = {mem1: mem1_init, mem2: mem2_init}

# now run the simulation like before. Note the adding of the memory
# value map.
print("---------memories----------")
print(pyrtl.working_block())
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace, memory_value_map=memvals)
for cycle in range(len(simvals['we'])):
    sim.step({k: int(v[cycle]) for k, v in simvals.items()})
sim_trace.render_trace()

toFirrtl_new.translate_to_firrtl(pyrtl.working_block(), "./firrtl_result.fir")
with open('./firrtl_result.fir', 'r') as myfile:
    firrtl_str = myfile.read()

toFirrtl_new.wrap_firrtl_test(sim_trace, pyrtl.working_block(), firrtl_str, "example6tester", "/Users/shannon/Desktop/firrtl-interpreter/src/test/scala/firrtl_interpreter/")

# cleanup in preparation for the rom example
pyrtl.reset_working_block()

# --- Part 2: ROMs -----------------------------------------------------------

counter = pyrtl.Register(bitwidth=3, name='counter')
sum, carry_out = ripple_add(counter, pyrtl.Const("1'b1"))
counter.next <<= sum

# A couple new things in the above code.  The two remaining types of basic
# WireVectors, Const and Register, both  appear.  Const, unsurprisingly, is just for
# holding constants (such as the 0 in ripple_add), but here we create one directly
# from a Verilog-like string which includes both the value and the bitwidth.
# Registers are just like wires, except their updates are delayed to the next
# clock cycle.  This is made explicit in the syntax through the property '.next'
# which should always be set for registers.  In this simple example, we take
# counter next cycle equal to counter this cycle plus one.

# Now let's run the bugger.  No need for inputs, as it doesn't have any.
# Finally we'll print the trace to the screen and check that it counts up correctly.
print(pyrtl.working_block())


sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace)
for cycle in range(20):
    sim.step({})
    assert sim.value[counter] == cycle % 8
sim_trace.render_trace()

# all done.

toFirrtl_new.translate_to_firrtl(pyrtl.working_block(), "./firrtl_result.fir")
with open('./firrtl_result.fir', 'r') as myfile:
    firrtl_str = myfile.read()

toFirrtl_new.wrap_firrtl_test(sim_trace, pyrtl.working_block(), firrtl_str, "example2tester", "/Users/shannon/Desktop/firrtl-interpreter/src/test/scala/firrtl_interpreter/")

critical_path = pyrtl.timing_critical_path(timing_map)

        pyrtl.synthesize()
        pyrtl.optimize()

        block = pyrtl.working_block()
        timing_map = pyrtl.timing_analysis(block)
        timing_max_length = pyrtl.timing_max_length(timing_map)
        if opt_timing_val is not None:
            self.assertEqual(timing_max_length, opt_timing_val)
        critical_path = pyrtl.timing_critical_path(timing_map)

        pyrtl.and_inverter_synth()
        pyrtl.optimize()

        block = pyrtl.working_block()
        timing_map = pyrtl.timing_analysis(block)
        timing_max_length = pyrtl.timing_max_length(timing_map)
        self.assertEqual(self.num_net_of_type('|', block), 0)
        self.assertEqual(self.num_net_of_type('^', block), 0)

        pyrtl.nand_synth()
        pyrtl.optimize()

        block = pyrtl.working_block()
        timing_map = pyrtl.timing_analysis(block)
        timing_max_length = pyrtl.timing_max_length(timing_map)
        block.sanity_check()
        self.assertEqual(self.num_net_of_type('|', block), 0)
        self.assertEqual(self.num_net_of_type('&', block), 0)
        self.assertEqual(self.num_net_of_type('^', block), 0)

def test_valid_slices(self):
        self.valid_slice(8, slice(6))
        self.valid_slice(8, slice(1, 4))
        self.valid_slice(8, slice(1, 8))  # Yes, supplying a end index out of bounds is valid python
        self.valid_slice(8, slice(1, 2, 2))
        self.valid_slice(8, slice(1, 4, 2))
        self.valid_slice(8, slice(7, 1, -2))
        self.valid_slice(8, slice(-2))
        self.valid_slice(8, slice(-6, -2, 3))
        pyrtl.working_block().sanity_check()

def everything_t_procedure(self, timing_val=None, opt_timing_val=None):
        # if there is a nondefault timing val supplied, then it will check
        # to make sure that the timing matches
        # this is a subprocess to do the synth and timing
        block = pyrtl.working_block()
        timing_map = pyrtl.timing_analysis(block)
        timing_max_length = pyrtl.timing_max_length(timing_map)
        if timing_val is not None:
            self.assertEqual(timing_max_length, timing_val)
        critical_path = pyrtl.timing_critical_path(timing_map)

        pyrtl.synthesize()
        pyrtl.optimize()

        block = pyrtl.working_block()
        timing_map = pyrtl.timing_analysis(block)
        timing_max_length = pyrtl.timing_max_length(timing_map)
        if opt_timing_val is not None:
            self.assertEqual(timing_max_length, opt_timing_val)
        critical_path = pyrtl.timing_critical_path(timing_map)

        pyrtl.and_inverter_synth()
        pyrtl.optimize()

        block = pyrtl.working_block()
        timing_map = pyrtl.timing_analysis(block)
        timing_max_length = pyrtl.timing_max_length(timing_map)
        self.assertEqual(self.num_net_of_type('|', block), 0)
        self.assertEqual(self.num_net_of_type('^', block), 0)

        pyrtl.nand_synth()

def test_async_check_should_pass_with_select(self):
        memory = pyrtl.MemBlock(
                    bitwidth=self.bitwidth, 
                    addrwidth=self.addrwidth-1,
                    name='memory')
        self.output1 <<= memory[self.mem_read_address1[0:-1]]
        pyrtl.working_block().sanity_check()

def check_trace(self, correct_string):
        wtt = pyrtl.working_block().wirevector_subset(pyrtl.Output)
        sim_trace = pyrtl.SimulationTrace(wires_to_track=wtt)
        sim = self.sim(tracer=sim_trace)
        for i in range(8):
            sim.step({})
        output = six.StringIO()
        sim_trace.print_trace(output, compact=True)
        self.assertEqual(output.getvalue(), correct_string)

def sanity_error(self, msg):
        with self.assertRaisesRegexp(pyrtl.PyrtlError, msg):
            pyrtl.working_block().sanity_check()

def test_const_folding_basic_two_var_op_2(self):
        inwire = pyrtl.Input(bitwidth=1)
        constwire = pyrtl.Const(0, 1)
        outwire = pyrtl.Output()

        outwire <<= inwire | constwire
        pyrtl.optimize()
        # should remove the and block and replace it with a
        # wire net (to separate the const from the output)
        block = pyrtl.working_block(None)
        self.assertEqual(self.num_net_of_type('|', block), 0)
        self.assertEqual(self.num_net_of_type('w', block), 1)
        self.assertEqual(len(block.logic), 1)
        self.assertEqual(len(block.wirevector_set), 2)
        self.assertEqual(self.num_wire_of_type(pyrtl.wire.Const, block), 0)

b32 = sbox[a32]
	b33 = sbox[a33]

	out_vector = pyrtl.concat(b00, b01, b02, b03,
					b10, b11, b12, b13,
					b20, b21, b22, b23,
					b30, b31, b32, b33)

	return out_vector

# Hardware build.
aes_input = pyrtl.Input(bitwidth=128, name='aes_input')
aes_output = pyrtl.Output(bitwidth=128, name='aes_output')
aes_output <<= SubBytes(aes_input)

print pyrtl.working_block()
print 

sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace)

for cycle in range(1):
	sim.step({aes_input: 0x53})

sim_trace.render_trace(symbol_len=12, segment_size=5)