How to use the pyrtl.core.PyrtlInternalError function in pyrtl
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UCSBarchlab / PyRTL / pyrtl / core.py View on Github 
raise PyrtlInternalError('error, net must be of type LogicNet')
if not isinstance(net.args, tuple):
raise PyrtlInternalError('error, LogicNet args must be tuple')
if not isinstance(net.dests, tuple):
raise PyrtlInternalError('error, LogicNet dests must be tuple')
for w in net.args + net.dests:
self.sanity_check_wirevector(w)
if w not in self.wirevector_set:
raise PyrtlInternalError('error, net with unknown source "%s"' % w.name)
if w.block is not self:
raise PyrtlInternalError('error, net references different block')
# checks that input and output wirevectors are not misused
for w in net.dests:
if isinstance(w, wire.Input):
raise PyrtlInternalError('error, Inputs cannot be destinations to a net')
for w in net.args:
if isinstance(w, wire.Output):
raise PyrtlInternalError('error, Outputs cannot be arguments for a net')
if net.op not in self.legal_ops:
raise PyrtlInternalError('error, net op "%s" not from acceptable set %s' %
(net.op, self.legal_ops))
# operation specific checks on arguments
if net.op in 'w~rs' and len(net.args) != 1:
raise PyrtlInternalError('error, op only allowed 1 argument')
if net.op in '&|^+-*<>=' and len(net.args) != 2:
raise PyrtlInternalError('error, op only allowed 2 arguments')
if net.op in 'x' and len(net.args) != 3:
raise PyrtlInternalError('error, op only allowed 3 arguments')
if net.op in '&|^+-*<>=' and len(set(x.bitwidth for x in net.args)) > 1:def sanity_check_net(self, net):
""" Check that net is a valid LogicNet. """
# general sanity checks that apply to all operations
if not isinstance(net, LogicNet):
raise PyrtlInternalError('error, net must be of type LogicNet')
if not isinstance(net.args, tuple):
raise PyrtlInternalError('error, LogicNet args must be tuple')
if not isinstance(net.dests, tuple):
raise PyrtlInternalError('error, LogicNet dests must be tuple')
for w in net.args + net.dests:
self.sanity_check_wirevector(w)
if w not in self.wirevector_set:
raise PyrtlInternalError('error, net with unknown source "%s"' % w.name)
if w.block is not self:
raise PyrtlInternalError('error, net references different block')
# checks that input and output wirevectors are not misused
for w in net.dests:
if isinstance(w, wire.Input):
raise PyrtlInternalError('error, Inputs cannot be destinations to a net')
for w in net.args:
if isinstance(w, wire.Output):
raise PyrtlInternalError('error, Outputs cannot be arguments for a net')
if net.op not in self.legal_ops:for w in net.dests:
if isinstance(w, wire.Input):
raise PyrtlInternalError('error, Inputs cannot be destinations to a net')
for w in net.args:
if isinstance(w, wire.Output):
raise PyrtlInternalError('error, Outputs cannot be arguments for a net')
if net.op not in self.legal_ops:
raise PyrtlInternalError('error, net op "%s" not from acceptable set %s' %
(net.op, self.legal_ops))
# operation specific checks on arguments
if net.op in 'w~rs' and len(net.args) != 1:
raise PyrtlInternalError('error, op only allowed 1 argument')
if net.op in '&|^+-*<>=' and len(net.args) != 2:
raise PyrtlInternalError('error, op only allowed 2 arguments')
if net.op in 'x' and len(net.args) != 3:
raise PyrtlInternalError('error, op only allowed 3 arguments')
if net.op in '&|^+-*<>=' and len(set(x.bitwidth for x in net.args)) > 1:
raise PyrtlInternalError('error, args have mismatched bitwidths')
if net.op == 'x' and net.args[1].bitwidth != net.args[2].bitwidth:
raise PyrtlInternalError('error, args have mismatched bitwidths')
if net.op == 'x' and net.args[0].bitwidth != 1:
raise PyrtlInternalError('error, mux select must be a single bit')
if net.op in 'm@' and net.args[0].bitwidth != net.op_param[1].addrwidth:
raise PyrtlInternalError('error, mem addrwidth mismatch')
if net.op == '@' and net.args[1].bitwidth != net.op_param[1].bitwidth:
raise PyrtlInternalError('error, mem bitwidth mismatch')
if net.op == '@' and net.args[2].bitwidth != 1:
raise PyrtlInternalError('error, mem write enable must be 1 bit')
# operation specific checks on op_paramsif not isinstance(net.op_param[1], memblock.MemBlock):
raise PyrtlInternalError('error, mem op requires second operand MemBlock')
# check destination validity
if net.op in 'w~&|^r' and net.dests[0].bitwidth > net.args[0].bitwidth:
raise PyrtlInternalError('error, upper bits of destination unassigned')
if net.op in '<>=' and net.dests[0].bitwidth != 1:
raise PyrtlInternalError('error, destination should be of bitwidth=1')
if net.op in '+-' and net.dests[0].bitwidth > net.args[0].bitwidth + 1:
raise PyrtlInternalError('error, upper bits of destination unassigned')
if net.op == '*' and net.dests[0].bitwidth > 2 * net.args[0].bitwidth:
raise PyrtlInternalError('error, upper bits of destination unassigned')
if net.op == 'x' and net.dests[0].bitwidth > net.args[1].bitwidth:
raise PyrtlInternalError('error, upper bits of mux output undefined')
if net.op == 'c' and net.dests[0].bitwidth > sum(x.bitwidth for x in net.args):
raise PyrtlInternalError('error, upper bits of concat output undefined')
if net.op == 's' and net.dests[0].bitwidth > len(net.op_param):
raise PyrtlInternalError('error, upper bits of select output undefined')
if net.op == 'm' and net.dests[0].bitwidth != net.op_param[1].bitwidth:
raise PyrtlInternalError('error, mem read dest bitwidth mismatch')raise PyrtlInternalError('error, mem write enable must be 1 bit')
# operation specific checks on op_params
if net.op in 'w~&|^+-*<>=xcr' and net.op_param is not None:
raise PyrtlInternalError('error, op_param should be None')
if net.op == 's':
if not isinstance(net.op_param, tuple):
raise PyrtlInternalError('error, select op requires tuple op_param')
for p in net.op_param:
if p < 0 or p >= net.args[0].bitwidth:
raise PyrtlInternalError('error, op_param out of bounds')
if net.op in 'm@':
if not isinstance(net.op_param, tuple):
raise PyrtlInternalError('error, mem op requires tuple op_param')
if len(net.op_param) != 2:
raise PyrtlInternalError('error, mem op requires 2 op_params in tuple')
if not isinstance(net.op_param[0], int):
raise PyrtlInternalError('error, mem op requires first operand as int')
if not isinstance(net.op_param[1], memblock.MemBlock):
raise PyrtlInternalError('error, mem op requires second operand MemBlock')
# check destination validity
if net.op in 'w~&|^r' and net.dests[0].bitwidth > net.args[0].bitwidth:
raise PyrtlInternalError('error, upper bits of destination unassigned')
if net.op in '<>=' and net.dests[0].bitwidth != 1:
raise PyrtlInternalError('error, destination should be of bitwidth=1')
if net.op in '+-' and net.dests[0].bitwidth > net.args[0].bitwidth + 1:
raise PyrtlInternalError('error, upper bits of destination unassigned')
if net.op == '*' and net.dests[0].bitwidth > 2 * net.args[0].bitwidth:
raise PyrtlInternalError('error, upper bits of destination unassigned')
if net.op == 'x' and net.dests[0].bitwidth > net.args[1].bitwidth:
raise PyrtlInternalError('error, upper bits of mux output undefined')def sanity_check_net(self, net):
""" Check that net is a valid LogicNet. """
# general sanity checks that apply to all operations
if not isinstance(net, LogicNet):
raise PyrtlInternalError('error, net must be of type LogicNet')
if not isinstance(net.args, tuple):
raise PyrtlInternalError('error, LogicNet args must be tuple')
if not isinstance(net.dests, tuple):
raise PyrtlInternalError('error, LogicNet dests must be tuple')
for w in net.args + net.dests:
self.sanity_check_wirevector(w)
if w not in self.wirevector_set:
raise PyrtlInternalError('error, net with unknown source "%s"' % w.name)
if w.block is not self:
raise PyrtlInternalError('error, net references different block')
# checks that input and output wirevectors are not misused
for w in net.dests:
if isinstance(w, wire.Input):
raise PyrtlInternalError('error, Inputs cannot be destinations to a net')
for w in net.args:
if isinstance(w, wire.Output):
raise PyrtlInternalError('error, Outputs cannot be arguments for a net')raise PyrtlInternalError('error, args have mismatched bitwidths')
if net.op == 'x' and net.args[0].bitwidth != 1:
raise PyrtlInternalError('error, mux select must be a single bit')
if net.op in 'm@' and net.args[0].bitwidth != net.op_param[1].addrwidth:
raise PyrtlInternalError('error, mem addrwidth mismatch')
if net.op == '@' and net.args[1].bitwidth != net.op_param[1].bitwidth:
raise PyrtlInternalError('error, mem bitwidth mismatch')
if net.op == '@' and net.args[2].bitwidth != 1:
raise PyrtlInternalError('error, mem write enable must be 1 bit')
# operation specific checks on op_params
if net.op in 'w~&|^+-*<>=xcr' and net.op_param is not None:
raise PyrtlInternalError('error, op_param should be None')
if net.op == 's':
if not isinstance(net.op_param, tuple):
raise PyrtlInternalError('error, select op requires tuple op_param')
for p in net.op_param:
if p < 0 or p >= net.args[0].bitwidth:
raise PyrtlInternalError('error, op_param out of bounds')
if net.op in 'm@':
if not isinstance(net.op_param, tuple):
raise PyrtlInternalError('error, mem op requires tuple op_param')
if len(net.op_param) != 2:
raise PyrtlInternalError('error, mem op requires 2 op_params in tuple')
if not isinstance(net.op_param[0], int):
raise PyrtlInternalError('error, mem op requires first operand as int')
if not isinstance(net.op_param[1], memblock.MemBlock):
raise PyrtlInternalError('error, mem op requires second operand MemBlock')
# check destination validity
if net.op in 'w~&|^r' and net.dests[0].bitwidth > net.args[0].bitwidth:
raise PyrtlInternalError('error, upper bits of destination unassigned')# check destination validity
if net.op in 'w~&|^r' and net.dests[0].bitwidth > net.args[0].bitwidth:
raise PyrtlInternalError('error, upper bits of destination unassigned')
if net.op in '<>=' and net.dests[0].bitwidth != 1:
raise PyrtlInternalError('error, destination should be of bitwidth=1')
if net.op in '+-' and net.dests[0].bitwidth > net.args[0].bitwidth + 1:
raise PyrtlInternalError('error, upper bits of destination unassigned')
if net.op == '*' and net.dests[0].bitwidth > 2 * net.args[0].bitwidth:
raise PyrtlInternalError('error, upper bits of destination unassigned')
if net.op == 'x' and net.dests[0].bitwidth > net.args[1].bitwidth:
raise PyrtlInternalError('error, upper bits of mux output undefined')
if net.op == 'c' and net.dests[0].bitwidth > sum(x.bitwidth for x in net.args):
raise PyrtlInternalError('error, upper bits of concat output undefined')
if net.op == 's' and net.dests[0].bitwidth > len(net.op_param):
raise PyrtlInternalError('error, upper bits of select output undefined')
if net.op == 'm' and net.dests[0].bitwidth != net.op_param[1].bitwidth:
raise PyrtlInternalError('error, mem read dest bitwidth mismatch')pyrtl
RTL-level Hardware Design and Simulation Toolkit
Package Health Score
70 / 100Popular pyrtl functions
- pyrtl.concat
- pyrtl.concat_list
- pyrtl.Const
- pyrtl.core.LogicNet
- pyrtl.core.PyrtlInternalError
- pyrtl.core.working_block
- pyrtl.Input
- pyrtl.mux
- pyrtl.Output
- pyrtl.PyrtlError
- pyrtl.pyrtlexceptions.PyrtlError
- pyrtl.pyrtlexceptions.PyrtlInternalError
- pyrtl.Register
- pyrtl.reset_working_block
- pyrtl.Simulation
- pyrtl.SimulationTrace
- pyrtl.wire.Const
- pyrtl.wire.WireVector
- pyrtl.WireVector
- pyrtl.working_block