How to use the pyrtl.Input function in pyrtl

def test_prng_lfsr(self):
        seed = pyrtl.Input(127, 'seed')
        load, req = pyrtl.Input(1, 'load'), pyrtl.Input(1, 'req')
        rand = pyrtl.Output(128, 'rand')
        rand <<= prngs.prng_lfsr(128, load, req, seed)
        sim_trace = pyrtl.SimulationTrace()
        sim = pyrtl.Simulation(tracer=sim_trace)
        in_vals = [random.randrange(1, 2**127) for i in range(5)]

        for trial in range(5):
            true_val = 0
            for bit in islice(TestPrngs.fibonacci_lfsr(in_vals[trial]), 128):
                true_val = true_val << 1 | bit
            sim.step({'load': 1, 'req': 0, 'seed': in_vals[trial]})
            sim.step({'load': 0, 'req': 1, 'seed': 0x0})
            sim.step({'load': 0, 'req': 0, 'seed': 0x0})
            circuit_out = sim.inspect(rand)
            self.assertEqual(circuit_out, true_val,
                             "\nAssertion failed on trial {}\nExpected value: {}\nGotten value: {}"

def test_invalid_inspect(self):
        a = pyrtl.Input(8, 'a')
        sim_trace = pyrtl.SimulationTrace()
        sim = self.sim(tracer=sim_trace)
        sim.step({a: 28})
        with self.assertRaises(KeyError):
            sim.inspect('asd')

def test_aes_state_machine(self):
        # self.longMessage = True

        aes_key = pyrtl.Input(bitwidth=128, name='aes_key')
        reset = pyrtl.Input(1)
        ready = pyrtl.Output(1, name='ready')

        decrypt_ready, decrypt_out = self.aes.decryption_statem(self.in_vector, aes_key, reset)
        self.out_vector <<= decrypt_out
        ready <<= decrypt_ready

        sim_trace = pyrtl.SimulationTrace()
        sim = pyrtl.Simulation(tracer=sim_trace)

        sim.step({
            self.in_vector: 0x69c4e0d86a7b0430d8cdb78070b4c55a,
            aes_key: 0x000102030405060708090a0b0c0d0e0f,
            reset: 1
        })

def test_function_RomBlock_with_optimization(self):

        def rom_data_function(add):
            return int((add + 5)/2)

        pyrtl.reset_working_block()
        self.bitwidth = 4
        self.addrwidth = 4
        self.output1 = pyrtl.Output(self.bitwidth, "o1")
        self.output2 = pyrtl.Output(self.bitwidth, "o2")
        # self.output3 = pyrtl.Output(self.bitwidth, "o3")
        # self.read_out = pyrtl.WireVector(self.bitwidth)
        self.read_addr1 = pyrtl.Input(self.addrwidth)
        self.read_addr2 = pyrtl.Input(self.addrwidth)
        self.rom = pyrtl.RomBlock(bitwidth=self.bitwidth, addrwidth=self.addrwidth,
                                  name='rom', romdata=rom_data_function)
        # self.read_out <<= self.rom[self.read_addr1]
        # self.output1 <<= self.read_out - 1
        self.output1 <<= self.rom[self.read_addr1]
        self.output2 <<= self.rom[self.read_addr2]

        pyrtl.synthesize()
        pyrtl.optimize()
        # build the actual simulation environment
        self.sim_trace = pyrtl.SimulationTrace()
        self.sim = pyrtl.FastSimulation(tracer=self.sim_trace)

        input_signals = {}
        for i in range(0, 5):
            input_signals[i] = {self.read_addr1: i, self.read_addr2: 2*i}

def test_inspect_mem(self):
        a = pyrtl.Input(8, 'a')
        b = pyrtl.Input(8, 'b')
        mem = pyrtl.MemBlock(8, 8, 'mem')
        mem[b] <<= a
        sim_trace = pyrtl.SimulationTrace()
        sim = self.sim(tracer=sim_trace)
        self.assertEqual(sim.inspect_mem(mem), {})
        sim.step({a: 3, b: 23})
        self.assertEqual(sim.inspect_mem(mem), {23: 3})

import pyrtl

router_id = pyrtl.Input(4,'router_id')
dest_id = pyrtl.Input(4,'dest_id')

# 	-------------------------
#	|G|N|S|E|W|port 3bits|VC|		9bits
#	-------------------------
#	port N = 0 | S = 1 | E = 2 | W= 3 | Self = 4 |
#
port = pyrtl.Input(3,'port')	#port which is giving Input signals

go_x=pyrtl.Output(9,'go_x')	#the X co-ordinate Request	##select X or Y request || X first then Y
go_y=pyrtl.Output(9,'go_y')	#the Y co-ordinate Request
x=pyrtl.WireVector(2,'x')	#X co-ordinate of the route
y=pyrtl.WireVector(2,'y')	#Y co-ordinate of the route
vc = pyrtl.Input(1,'vc')	# Virtual channel

x<<=pyrtl.mux((router_id[0:2]>dest_id[0:2]),truecase=router_id[0:2]-dest_id[0:2],falsecase=dest_id[0:2]-router_id[0:2])
y<<=pyrtl.mux((router_id[2:4]>dest_id[2:4]),truecase=router_id[2:4]-dest_id[2:4],falsecase=dest_id[2:4]-router_id[2:4])

""" Example 3:  A State Machine built with conditional_assignment
    In this example we describe how conditional_assignment works in the context of
    a vending machine that will dispense an item when it has received 4 tokens.
    If a refund is requested, it returns the tokens.
"""

import pyrtl

token_in = pyrtl.Input(1, 'token_in')
req_refund = pyrtl.Input(1, 'req_refund')
dispense = pyrtl.Output(1, 'dispense')
refund = pyrtl.Output(1, 'refund')
state = pyrtl.Register(3, 'state')

# First new step, let's enumerate a set of constant to serve as our states
WAIT, TOK1, TOK2, TOK3, DISPENSE, REFUND = [pyrtl.Const(x, bitwidth=3) for x in range(6)]

# Now we could build a state machine using just the registers and logic discussed
# in the earlier examples, but doing operations *conditional* on some input is a pretty
# fundamental operation in hardware design.  PyRTL provides an instance "conditional_assignment"
# to provide a predicated update to a registers, wires, and memories.
#
# Conditional assignments are specified with a "|=" instead of a "<<=" operator.  The
# conditional assignment is only value in the context of a condition, and update to those
# values only happens when that condition is true.  In hardware this is implemented

def testadder():

	a,b,c = Input(1,'a'), Input(1,'b'), Input(1,'c')
	sum, cout = Output(1,'sum'), Output(1,'cout')
	sum <<= a ^ b ^ c
	cout <<= a & b | a & c | b & c

	a.DIST0, a.DIST1 = .15, .15
	b.DIST0, b.DIST1 = .15, .15
	c.DIST0, c.DIST1 = .15, .15

	print mibound(pyrtl.working_block())

	for i in range(10):
		for x in (a,b,c):
			x.DIST0 = np.random.rand()
			x.DIST1 = np.random.rand()
		print mibound(pyrtl.working_block())

def test_buffer():

    buffer_addrwidth = 2
    buffer_bitwidth = 8
    write_enable = pyrtl.Input(1,'write_enable')
    read_enable = pyrtl.Input(1,'read_enable')
    data_in = pyrtl.Input(buffer_bitwidth,'data_in')
    data_out = pyrtl.Output(buffer_bitwidth,'data_out')
    valid = pyrtl.Output(1,'valid')
    full = pyrtl.Output(1,'full')

    read_output, valid_output, full_output = surfnoc_buffer(buffer_bitwidth, buffer_addrwidth, data_in, write_enable, read_enable)
    data_out <<= read_output
    valid <<= valid_output
    full <<= full_output

    simvals = {
	    write_enable: "111111110000111100000001111",
	    data_in:      "123456780000678900000001234",
	    read_enable:  "000000001111000001111111111"
	}
	
    sim_trace=pyrtl.SimulationTrace()

a21 = in_vector[48:56]
    a22 = in_vector[40:48]
    a23 = in_vector[32:40]
    a30 = in_vector[24:32]
    a31 = in_vector[16:24]
    a32 = in_vector[8:16]
    a33 = in_vector[0:8]
    
    out_vector = pyrtl.concat(a00, a01, a02, a03,
                      a11, a12, a13, a10,
                      a22, a23, a20, a21,
                      a33, a30, a31, a32)
    return out_vector

# Hardware build.
aes_input = pyrtl.Input(bitwidth=128, name='aes_input')
aes_output = pyrtl.Output(bitwidth=128, name='aes_output')
aes_output <<= aes_shift_rows(aes_input)

print pyrtl.working_block()
print

sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace)

for cycle in range(1):
    sim.step({aes_input: 35})

sim_trace.render_trace(symbol_len=5, segment_size=5)