How to use the pyrtl.Simulation function in pyrtl

def check_trace(self, correct_string):
        sim_trace = pyrtl.SimulationTrace()
        sim = pyrtl.Simulation(tracer=sim_trace)
        for i in range(8):
            sim.step({})
        output = io.StringIO()
        sim_trace.print_trace(output)
        print(output.getvalue())
        self.assertEqual(output.getvalue(), correct_string)

# with a:
#     r.next |= 1        <-- when a is true
#     with d:
#         r2.next |= 2   <-- when a and d are true
#     with otherwise:
#         r2.next |= 3   <-- when a is true and d is false
# with b == c:
#     r.next |= 0        <-- when a is not true and b & c is true

# Now let's build and test our state machine.

print(pyrtl.working_block())
toFirrtl_new.translate_to_firrtl(pyrtl.working_block(), "./firrtl_result.fir")

sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace)

# Rather than just give some random inputs, let's specify some specific 1 bit values.  Recall
# that the sim.step method takes a dictionary mapping inputs to their values.  We could just
# specify the input set directly as a dictionary but it gets pretty ugly -- let's use some python
# to parse them up.

sim_inputs = {
    'token_in':   '0010100111010000',
    'req_refund': '1100010000000000'
    }

for cycle in range(len(sim_inputs['token_in'])):
    sim.step({w: int(v[cycle]) for w, v in sim_inputs.items()})

# also, to make our input/output easy to reason about let's specify an order to the traces
sim_trace.render_trace(trace_list=['token_in', 'req_refund', 'state', 'dispense', 'refund'])

def test_verilog_testbench_does_not_throw_error(self):
        zero = pyrtl.Input(1, 'zero')
        counter_output = pyrtl.Output(3, 'counter_output')
        counter = pyrtl.Register(3, 'counter')
        counter.next <<= pyrtl.mux(zero, counter + 1, 0)
        counter_output <<= counter
        sim_trace = pyrtl.SimulationTrace([counter_output, zero])
        sim = pyrtl.Simulation(tracer=sim_trace)
        for cycle in range(15):
            sim.step({zero: random.choice([0, 0, 0, 1])})
        with io.StringIO() as tbfile:
            pyrtl.output_verilog_testbench(tbfile, sim_trace)

def check_trace(self, correct_string):
        # pyrtl.synthesize()
        sim_trace = pyrtl.SimulationTrace()
        sim = pyrtl.Simulation(tracer=sim_trace)
        for i in range(8):
            sim.step({})
        output = io.StringIO()
        sim_trace.print_trace(output)
        self.assertEqual(output.getvalue(), correct_string)

def mult_t_base(self, len_a, len_b):
        # Creating the logic nets
        a, b = pyrtl.Input(len_a, "a"), pyrtl.Input(len_b, "b")
        product = pyrtl.Output(name="product")
        product <<= pyrtl.corecircuits._basic_mult(a, b)

        self.assertEqual(len(product), len_a + len_b)

        # creating the testing values and the correct results
        xvals = [int(random.uniform(0, 2**len_a-1)) for i in range(20)]
        yvals = [int(random.uniform(0, 2**len_b-1)) for i in range(20)]
        true_result = [i * j for i, j in zip(xvals, yvals)]

        # Setting up and running the tests
        sim_trace = pyrtl.SimulationTrace()
        sim = pyrtl.Simulation(tracer=sim_trace)
        for cycle in range(len(xvals)):
            sim.step({a: xvals[cycle], b: yvals[cycle]})

        # Extracting the values and verifying correctness
        multiplier_result = sim_trace.trace[product]
        self.assertEqual(multiplier_result, true_result)

#print infoTable
    #print immortalHeap
    #print itables
    #print code

    #print "itables id: {}".format(infoTable.stored_net.op_param[0])
    #print "iheap id: {}".format(immortalHeap.stored_net.op_param[0])

    #print find_cycle(pyrtl.working_block())

    
    if itables is not None and code is not None:
        simlen = 15
        sim_trace = pyrtl.SimulationTrace()
        sim = pyrtl.Simulation(tracer=sim_trace, 
                               memory_value_map={infoTable: itables, immortalHeap: code})
        for cycle in range(simlen):
            sim.step({})
        sim_trace.render_trace()

dout |= din
		with pyrtl.otherwise:
			dout |= 0 
	return dout[24-offset:32-offset]

# Test: collects only the 8 LSBs (after relu)
relu_in = pyrtl.Register(bitwidth=32, name='din')
relu_in.next <<= 300
offset = 24
dout = relu_nrml(relu_in, offset)
relu_out = pyrtl.Register(bitwidth=8, name='dout')
relu_out.next <<= dout 

# simulate the instantiated design for 15 cycles
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace)
for cyle in range(35):
	sim.step({})
sim_trace.render_trace()

# because the values in the wires are not populated during *creation* time

# If we want to check the result of the first addition, we can connect an output wire
# to the result wire of the first adder

debug_out = pyrtl.Output(9, "debug_out")
debug_out <<= add1_out

# now simulate the circuit.  Let's create some random inputs to feed our adder.

vals1 = [int(2**random.uniform(1, 8) - 2) for _ in range(20)]
vals2 = [int(2**random.uniform(1, 8) - 2) for _ in range(20)]
vals3 = [int(2**random.uniform(1, 8) - 2) for _ in range(20)]

sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace)
for cycle in range(len(vals1)):
    sim.step({
        in1: vals1[cycle],
        in2: vals2[cycle],
        in3: vals3[cycle]})

# in order to get the result data, you do not need to print a waveform of the trace
# You always have the option to just pull the data out of the tracer directly

print("in1:       ", str(sim_trace.trace[in1]))
print("in2:       ", str(sim_trace.trace[in2]))
print("debug_out: ", str(sim_trace.trace[debug_out]))

# Below, I am using the ability to directly retrieve the trace data to
# verify the correctness of the first adder

y<<=pyrtl.mux((router_id[2:4]>dest_id[2:4]),truecase=router_id[2:4]-dest_id[2:4],falsecase=dest_id[2:4]-router_id[2:4])
x1 = pyrtl.mux(((x==3)|(dest_id[0:2]>router_id[0:2])),truecase=18,falsecase=pyrtl.mux(router_id[0:2]>dest_id[0:2],truecase=17,falsecase=pyrtl.mux(((x==0)&(y==0)),truecase=31, falsecase=00000)))
y1 = pyrtl.mux(((y==3)|(dest_id[2:4]>router_id[2:4])),truecase=24,falsecase=pyrtl.mux(router_id[2:4]>dest_id[2:4],truecase=20,falsecase=pyrtl.mux(((y==0)&(x==0)),truecase=31,falsecase=00000)))


go_x <<= pyrtl.concat(x1,port,vc)
go_y <<= pyrtl.concat(y1,port,vc)

simvals ={
        router_id:[3,9,15,15,2,0,0],
	dest_id:[3,3,0,4,0,1,4],
	port:[0,1,2,3,4,2,1],
	vc: [0,1,0,1,0,1,1] 
}
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace)
for cycle in xrange(len(simvals[dest_id])):
    sim.step({k: v[cycle] for k,v in simvals.items()    })
sim_trace.render_trace(symbol_len=7)