How to use the pyrtl.reset_working_block function in pyrtl

def setUp(self):
        pyrtl.reset_working_block()

def setUp(self):
        pyrtl.reset_working_block()
        # test with '101' in binary, which should be
        # 5 for an unsigned operation and should be
        # -3 for an signed operation
        self.c = pyrtl.Const(0b101,bitwidth=3)
        self.r = pyrtl.Register(bitwidth=3)
        self.o = pyrtl.Output(bitwidth=4, name='o')
        self.r.next <<= self.r+1

def test_undriven_net(self):
        w = pyrtl.WireVector(name='testwire', bitwidth=3)
        self.assertRaises(pyrtl.PyrtlError, pyrtl.working_block().sanity_check)
        pyrtl.reset_working_block()
        r = pyrtl.Register(3)
        self.assertRaises(pyrtl.PyrtlError, pyrtl.working_block().sanity_check)
        pyrtl.reset_working_block()
        o = pyrtl.Output(3)
        self.assertRaises(pyrtl.PyrtlError, pyrtl.working_block().sanity_check)

def setUp(self):
        pyrtl.reset_working_block()

def setUp(self):
        pyrtl.reset_working_block()
        self.in1, self.in2 = (pyrtl.Input(8, "in"+str(i)) for i in range(1, 3))
        self.out = pyrtl.Output(9, "out")

def setUp(self):
        pyrtl.reset_working_block()
        self.bitwidth = 3
        self.addrwidth = 5
        self.output1 = pyrtl.Output(self.bitwidth, "output1")
        self.output2 = pyrtl.Output(self.bitwidth, "output2")
        self.mem_read_address1 = pyrtl.Input(self.addrwidth, name='mem_read_address1')
        self.mem_read_address2 = pyrtl.Input(self.addrwidth, name='mem_read_address2')
        self.mem_write_address = pyrtl.Input(self.addrwidth, name='mem_write_address')
        self.mem_write_data = pyrtl.Input(self.bitwidth, name='mem_write_data')
        self.memory = pyrtl.MemBlock(bitwidth=self.bitwidth, addrwidth=self.addrwidth,
                                     name='self.memory')

def setUp(self):
        pyrtl.reset_working_block()
        self.bitwidth = 3
        self.addrwidth = 4
        self.output1 = pyrtl.Output(self.bitwidth, "o1")
        self.output2 = pyrtl.Output(self.bitwidth, "o2")
        self.read_addr1 = pyrtl.Input(self.addrwidth)
        self.read_addr2 = pyrtl.Input(self.addrwidth)
        self.write_addr = pyrtl.Input(self.addrwidth)
        self.write_data = pyrtl.Input(self.bitwidth)
        self.rom = pyrtl.MemBlock(bitwidth=self.bitwidth, addrwidth=self.addrwidth,
                                  name='rom')
        self.output1 <<= self.rom[self.read_addr1]
        self.output2 <<= self.rom[self.read_addr2]
        self.rom[self.write_addr] <<= self.write_data

        # build the actual simulation environment
        self.sim_trace = pyrtl.SimulationTrace()

def setUp(self):
        pyrtl.reset_working_block()

self.assertEqual(sim_trace.trace[lfsr_out][disable_cycle + 1:],
                             [sim_trace.trace[lfsr_out][disable_cycle]]
                             * (19 - disable_cycle))

            true_val = TestLFSR.sw_galois_lfsr(seed_vals[1], bitwidth)
            sim.step({'seed': seed_vals[1], 'reset': 1, 'enable': 1})
            for cycle in range(1000 if bitwidth > 10 else 2**bitwidth - 1):
                sim.step({'seed': seed_vals[1], 'reset': 0, 'enable': 1})
                self.assertEqual(sim.value[lfsr_out], next(true_val))

            true_val = TestLFSR.sw_galois_lfsr(seed_vals[2], bitwidth)
            sim.step({'seed': seed_vals[2], 'reset': 1, 'enable': 1})
            for cycle in range(1000 if bitwidth > 10 else 2**bitwidth - 1):
                sim.step({'seed': seed_vals[2], 'reset': 0, 'enable': 1})
                self.assertEqual(sim.value[lfsr_out], next(true_val))
            pyrtl.reset_working_block()

def test_wire_from_another_block(self):
        w = pyrtl.Input(1)
        pyrtl.reset_working_block()
        self.bad_rtl_assert(w, self.RTLSampleException())