How to use the pyrtl.SimulationTrace function in pyrtl

def check_trace(self, correct_string):
        sim_trace = pyrtl.SimulationTrace()
        sim = pyrtl.Simulation(tracer=sim_trace)
        for i in range(8):
            sim.step({})
        output = six.StringIO()
        sim_trace.print_trace(output, compact=True)
        spaced_output = '  '.join(output.getvalue())  # add spaces to string
        self.assertEqual(spaced_output, correct_string)

"""
        Some simulations need to be careful when handling special names
        (eg Fastsim June 2016)
        """
        i = pyrtl.Input(8, '"182&!!!\n')
        o = pyrtl.Output(8, '*^*)#*$\'*')
        o2 = pyrtl.Output(8, 'test@+')
        w = pyrtl.WireVector(8, '[][[-=--09888')
        r = pyrtl.Register(8, '&@#)^#@^&(asdfkhafkjh')

        w <<= i
        r.next <<= i
        o <<= w
        o2 <<= r

        trace = pyrtl.SimulationTrace()
        sim = self.sim(tracer=trace)

        sim.step({i: 28})
        self.assertEqual(trace.trace[o.name], [28])
        sim.step({i: 233})
        self.assertEqual(trace.trace[o2.name], [0, 28])

def test_minus_sim_overflow(self):
        pyrtl.reset_working_block()
        i = pyrtl.Input(8, 'i')
        o = pyrtl.Output(name='o')
        o <<= i - 1

        tracer = pyrtl.SimulationTrace()
        sim = self.sim(tracer=tracer)
        sim.step({i: 1})
        sim.step({i: 0})
        self.assertEqual(tracer.trace['o'], [0, 0x1ff])

def check_trace(self, correct_string):
        sim_trace = pyrtl.SimulationTrace()
        sim = pyrtl.Simulation(tracer=sim_trace)
        for i in range(8):
            sim.step({})
        output = io.StringIO()
        sim_trace.print_trace(output, compact=True)
        self.assertEqual(output.getvalue(), correct_string)

def test_twos_comp_sim(self):
        self.out <<= self.in1 + self.in2
        sim_trace = pyrtl.SimulationTrace()
        sim = pyrtl.Simulation(tracer=sim_trace)
        for i in range(10):
            sim.step({
                'in1': i,
                'in2': libutils.twos_comp_repr(-2*i, 8)
            })
            self.assertEquals(-i, libutils.rev_twos_comp_repr(sim.inspect('out'), 8))

# here we are making use of that native add operation.  Let's dump this bad boy out
# to a verilog file and see what is looks like (here we are using StringIO just to
# print it to a string for demo purposes, most likely you will want to pass a normal
# open file).

print "--- PyRTL Representation ---"
print pyrtl.working_block()
print

print "--- Verilog for the Counter ---"
with io.BytesIO() as vfile:
    pyrtl.output_to_verilog(vfile)
    print vfile.getvalue()

print "--- Simulation Results ---"
sim_trace = pyrtl.SimulationTrace([counter_output, zero])
sim = pyrtl.Simulation(tracer=sim_trace)
for cycle in xrange(15):
    sim.step({zero: random.choice([0, 0, 0, 1])})
sim_trace.render_trace()

# We already did the "hard" work of generating a test input for this simulation so
# we might want to reuse that work when we take this design through a verilog toolchain.
# The function output_verilog_testbench grabs the inputs used in the simulation trace
# and sets them up in a standar verilog testbench.

print "--- Verilog for the TestBench ---"
with io.BytesIO() as tbfile:
    pyrtl.output_verilog_testbench(tbfile, sim_trace)
    print tbfile.getvalue()

# TOK2, TOK3, or DISPENSE.   Finally 5) not shown here, you can update multiple different registers,
# wires, and memories all under the same set of conditionals.

# A more artificial example might make it even more clear how these rules interact:
# with a:
#     r.next |= 1        <-- when a is true
#     with d:
#         r2.next |= 2   <-- when a and d are true
#     with otherwise:
#         r2.next |= 3   <-- when a is true and d is false
# with b == c:
#     r.next |= 0        <-- when a is not true and b & c is true

# Now let's build and test our state machine.

sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace)

# Rather than just give some random inputs, let's specify some specific 1 bit values.  Recall
# that the sim.step method takes a dictionary mapping inputs to their values.  We could just
# specify the input set directly as a dictionary but it gets pretty ugly -- let's use some python
# to parse them up.

sim_inputs = {
    'token_in':   '0010100111010000',
    'req_refund': '1100010000000000'
    }

for cycle in range(len(sim_inputs['token_in'])):
    sim.step({w: int(v[cycle]) for w, v in sim_inputs.items()})

# also, to make our input/output easy to reason about let's specify an order to the traces

'''simvals = {
        we:        "0011111111000000000000000",
        wdata:     "0012345678999000000000000",
        raddr:     "0000000000000000012345670",
        argswitch: "0000000000000010000000000"
    }

    '''
    simvals = {
        we:        "0111110000000000000000011111111000000000000000000",
        wdata:     "0123450000000000000000098765432000000000000000000",
        raddr:     "0000000123456700123456755555555012345670012345670",
        argswitch: "0000010000000010000000000000100000000001000000000"
    }

    sim_trace = pyrtl.SimulationTrace()
    sim = pyrtl.Simulation(tracer=sim_trace)
    for cycle in range(len(simvals[we])):
        sim.step({k:int(v[cycle]) for k,v in simvals.items()})
    sim_trace.render_trace()

def run(steps):
    sim_trace = pyrtl.SimulationTrace()
    sim = pyrtl.Simulation(tracer=sim_trace)
    for i in xrange(15):
        sim.step({})
    sim_trace.render_trace()