How to use the fusesoc.utils.unique_dirs function in fusesoc

def get_vpi(self, flags):
        self._debug("Getting VPI libraries for flags {}".format(flags))
        target = self._get_target(flags)
        vpi = []
        _vpi = self._get_vpi(flags)
        self._debug(" Matched VPI libraries {}".format([v for v in _vpi]))
        for k, v in sorted(_vpi.items()):
            vpi.append({'name'         : k,
                        'src_files'    : [f.name for f in v['src_files']],
                        'include_dirs' : utils.unique_dirs(v['inc_files']),
                        'libs'         : v['libs'],
            })
        return vpi

self._add_member('src_files'           , FileList, "Verilog source files for synthesis/simulation")
        self._add_member('include_files'       , FileList, "Verilog include files")
        self._add_member('tb_src_files'        , FileList, "Verilog source files that are only used in simulation. Visible to other cores")
        self._add_member('tb_private_src_files', FileList, "Verilog source files that are only used in the core's own testbench. Not visible to other cores")
        self._add_member('tb_include_files'    , FileList, "Testbench include files")
        self._add_member('file_type'           , str     , "Default file type of the files in fileset")

        if items:
            self.load_dict(items)
            if not self.file_type:
                self.file_type = "verilogSource"
            if self.include_files:
                self.include_dirs  += utils.unique_dirs(self.include_files)
            if self.tb_include_files:
                self.tb_include_dirs  += utils.unique_dirs(self.tb_include_files)

            self.export_files = self.src_files + self.include_files + self.tb_src_files + self.tb_include_files + self.tb_private_src_files

self.include_dirs = []

        self._add_member('verilator_options', StringList, "Verilator build options")
        self._add_member('src_files'        , FileList  , "Verilator testbench C/cpp/sysC source files")
        self._add_member('include_files'    , FileList  , "Verilator testbench C include files")
        self._add_member('define_files'     , PathList  , "Verilog include files containing `define directives to be converted to C #define directives in corresponding .h files")
        self._add_member('libs'             , PathList  , "External libraries linked with the generated model")

        self._add_member('tb_toplevel', FileList, 'Testbench top-level C/C++/SC file')
        self._add_member('source_type', str, 'Testbench source code language (Legal values are systemC, C, CPP. Default is C)')
        self._add_member('top_module' , str, 'verilog top-level module')
        self._add_member('cli_parser' , str, "Select CLI argument parser. Set to 'fusesoc' to handle parameter sections like other simulators. Set to 'passthrough' to send the arguments directly to the verilated model. Default is 'passthrough'")

        if items:
            self.load_dict(items)
            self.include_dirs  = unique_dirs(self.include_files)

self._add_member('src_files'           , FileList, "Verilog source files for synthesis/simulation")
        self._add_member('include_files'       , FileList, "Verilog include files")
        self._add_member('tb_src_files'        , FileList, "Verilog source files that are only used in simulation. Visible to other cores")
        self._add_member('tb_private_src_files', FileList, "Verilog source files that are only used in the core's own testbench. Not visible to other cores")
        self._add_member('tb_include_files'    , FileList, "Testbench include files")
        self._add_member('file_type'           , str     , "Default file type of the files in fileset")

        if items:
            self.load_dict(items)
            if not self.file_type:
                self.file_type = "verilogSource"
            if self.include_files:
                self.include_dirs  += utils.unique_dirs(self.include_files)
            if self.tb_include_files:
                self.tb_include_dirs  += utils.unique_dirs(self.tb_include_files)

            self.export_files = self.src_files + self.include_files + self.tb_src_files + self.tb_include_files + self.tb_private_src_files

self.include_dirs = []
        self.tb_include_dirs = []

        self._add_member('src_files'           , FileList, "Verilog source files for synthesis/simulation")
        self._add_member('include_files'       , FileList, "Verilog include files")
        self._add_member('tb_src_files'        , FileList, "Verilog source files that are only used in simulation. Visible to other cores")
        self._add_member('tb_private_src_files', FileList, "Verilog source files that are only used in the core's own testbench. Not visible to other cores")
        self._add_member('tb_include_files'    , FileList, "Testbench include files")
        self._add_member('file_type'           , str     , "Default file type of the files in fileset")

        if items:
            self.load_dict(items)
            if not self.file_type:
                self.file_type = "verilogSource"
            if self.include_files:
                self.include_dirs  += utils.unique_dirs(self.include_files)
            if self.tb_include_files:
                self.tb_include_dirs  += utils.unique_dirs(self.tb_include_files)

            self.export_files = self.src_files + self.include_files + self.tb_src_files + self.tb_include_files + self.tb_private_src_files

def __init__(self, items=None):
        super(VpiSection, self).__init__()

        self.include_dirs = []

        self._add_member('src_files'    , FileList, "C source files for VPI library")
        self._add_member('include_files', FileList, "C include files for VPI library")
        self._add_member('libs'         , StringList, "External libraries linked with the VPI library")

        if items:
            self.load_dict(items)
            if self.include_files:
                self.include_dirs  += unique_dirs(self.include_files)

            self.export_files = self.src_files + self.include_files

self._add_member('src_files'           , FileList, "Verilog source files for synthesis/simulation")
        self._add_member('include_files'       , FileList, "Verilog include files")
        self._add_member('tb_src_files'        , FileList, "Verilog source files that are only used in simulation. Visible to other cores")
        self._add_member('tb_private_src_files', FileList, "Verilog source files that are only used in the core's own testbench. Not visible to other cores")
        self._add_member('tb_include_files'    , FileList, "Testbench include files")
        self._add_member('file_type'           , str     , "Default file type of the files in fileset")

        if items:
            self.load_dict(items)
            if not self.file_type:
                self.file_type = "verilogSource"
            if self.include_files:
                self.include_dirs  += unique_dirs(self.include_files)
            if self.tb_include_files:
                self.tb_include_dirs  += unique_dirs(self.tb_include_files)

            self.export_files = self.src_files + self.include_files + self.tb_src_files + self.tb_include_files + self.tb_private_src_files

self._object_files = []

        self._add_member('verilator_options', StringList, "Verilator build options")
        self._add_member('src_files'        , FileList  , "Verilator testbench C/cpp/sysC source files")
        self._add_member('include_files'    , FileList  , "Verilator testbench C include files")
        self._add_member('define_files'     , PathList  , "Verilog include files containing `define directives to be converted to C #define directives in corresponding .h files")
        self._add_member('libs'             , PathList  , "External libraries linked with the generated model")

        self._add_member('tb_toplevel', str, 'Testbench top-level C/C++/SC file')
        self._add_member('source_type', str, 'Testbench source code language (Legal values are systemC, C, CPP. Default is C)')
        self._add_member('top_module' , str, 'verilog top-level module')
        self._add_member('cli_parser' , str, "Select CLI argument parser. Set to 'fusesoc' to handle parameter sections like other simulators. Set to 'passthrough' to send the arguments directly to the verilated model. Default is 'passthrough'")

        if items:
            self.load_dict(items)
            self.include_dirs  = unique_dirs(self.include_files)
            if self.src_files:
                self._object_files = [os.path.splitext(os.path.basename(s.name))[0]+'.o' for s in self.src_files]
                self.archive = True
                self.export_files += self.src_files + self.include_files