How to use the fusesoc.section.PathList function in fusesoc

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github optimsoc / optimsoc / fusesoc / section.py View on Github external
class StringList(list):
    def __new__(cls, *args, **kwargs):
        if not args:
            return list()
        else:
            return list(args[0].split())

class PathList(StringList):
    def __new__(cls, *args, **kwargs):
        if not args:
            return list()
        else:
            return [os.path.expandvars(p) for p in args[0].split()]

class FileList(PathList):
    def __new__(clk, *args, **kwargs):
        if not args:
            return list()
        else:
            return [File(p) for p in PathList(args[0])]

class VlnvList(StringList):
    def __new__(clk, *args, **kwargs):
        if not args:
            return list()
        else:
            return [Vlnv(p) for p in StringList(args[0])]

class EnumList(list):
    def __new__(cls, *args, **kwargs):
        if not args:
github olofk / fusesoc / fusesoc / section.py View on Github external
class StringList(list):
    def __new__(cls, *args, **kwargs):
        if not args:
            return list()
        else:
            return list(args[0].split())

class PathList(StringList):
    def __new__(cls, *args, **kwargs):
        if not args:
            return list()
        else:
            return [os.path.expandvars(p) for p in args[0].split()]

class FileList(PathList):
    def __new__(clk, *args, **kwargs):
        if not args:
            return list()
        else:
            return [File(p) for p in PathList(args[0])]

class EnumList(list):
    def __new__(cls, *args, **kwargs):
        if not args:
            return super(EnumList, cls).__new__(cls)
        else:
            values = kwargs['values']
            _args = args[0].split()
            _valid = []
            _invalid = []
            for arg in _args:
github optimsoc / optimsoc / fusesoc / section.py View on Github external
def _register_subclasses(parent):
    for cls in parent.__subclasses__():
        _register_subclasses(cls)
        if cls.TAG is None:
            continue
        SECTION_MAP[cls.TAG] = cls


_register_subclasses(Section)

if __name__ == "__main__":
    typenames = {str           : 'String',
                 FileList      : 'Space-separated list of files',
                 PathList      : 'Space-separated list of paths',
                 SimulatorList : 'Space-separated list',
                 SourceType    : 'String',
                 StringList    : 'Space-separated list',
                 VlnvList      : 'Space-separated list of VLNV identifiers',
                 list : 'List'}
    SECTION_TEMPLATE = """
{}
{}

[cols="2,1,5",options="header"]
|==============================
|Name | Type | Description
{}
|==============================

"""
github optimsoc / optimsoc / fusesoc / section.py View on Github external
def __init__(self, items=None):
        super(VerilatorSection, self).__init__()

        self.include_dirs = []

        self._add_member('verilator_options', StringList, "Verilator build options")
        self._add_member('src_files'        , FileList  , "Verilator testbench C/cpp/sysC source files")
        self._add_member('include_files'    , FileList  , "Verilator testbench C include files")
        self._add_member('define_files'     , PathList  , "Verilog include files containing `define directives to be converted to C #define directives in corresponding .h files")
        self._add_member('libs'             , PathList  , "External libraries linked with the generated model")

        self._add_member('tb_toplevel', FileList, 'Testbench top-level C/C++/SC file')
        self._add_member('source_type', str, 'Testbench source code language (Legal values are systemC, C, CPP. Default is C)')
        self._add_member('top_module' , str, 'verilog top-level module')
        self._add_member('cli_parser' , str, "Select CLI argument parser. Set to 'fusesoc' to handle parameter sections like other simulators. Set to 'passthrough' to send the arguments directly to the verilated model. Default is 'passthrough'")

        if items:
            self.load_dict(items)
            self.include_dirs  = unique_dirs(self.include_files)
github olofk / fusesoc / fusesoc / section.py View on Github external
def __init__(self, items=None):
        super(VhdlSection, self).__init__()

        self._add_member('src_files', PathList, "VHDL source files for simulation and synthesis")

        if items:
            self.load_dict(items)
            self.export_files = self.src_files
github optimsoc / optimsoc / fusesoc / section.py View on Github external
def __new__(clk, *args, **kwargs):
        if not args:
            return list()
        else:
            return [File(p) for p in PathList(args[0])]
github olofk / fusesoc / fusesoc / section.py View on Github external
def __new__(clk, *args, **kwargs):
        if not args:
            return list()
        else:
            return [File(p) for p in PathList(args[0])]
github olofk / fusesoc / fusesoc / section.py View on Github external
def _register_subclasses(parent):
    for cls in parent.__subclasses__():
        _register_subclasses(cls)
        if cls.TAG is None:
            continue
        SECTION_MAP[cls.TAG] = cls


_register_subclasses(Section)

if __name__ == "__main__":
    typenames = {str           : 'String',
                 FileList      : 'Space-separated list of files',
                 PathList      : 'Space-separated list of paths',
                 SimulatorList : 'Space-separated list',
                 SourceType    : 'String',
                 StringList    : 'Space-separated list',
                 list : 'List'}
    SECTION_TEMPLATE = """
{}
{}

[cols="2,1,5",options="header"]
|==============================
|Name | Type | Description
{}
|==============================

"""