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xdg_data_home = os.environ.get('XDG_DATA_HOME') or \
os.path.join(os.path.expanduser('~'),
'.local', 'share', 'fusesoc')
_repo_paths = []
for repo in REPOS:
default_dir = os.path.join(xdg_data_home, repo[0])
prompt = 'Directory to use for {} ({}) [{}] : '
if args.y:
cores_root = None
else:
cores_root = input(prompt.format(repo[0], repo[2], default_dir))
if not cores_root:
cores_root = default_dir
if os.path.exists(cores_root):
pr_warn("'{}' already exists".format(cores_root))
#TODO: Prompt for overwrite
else:
_repo_paths.append(cores_root)
pr_info("Initializing {}".format(repo[0]))
git_args = ['clone', repo[1], cores_root]
try:
Launcher('git', git_args).run()
except RuntimeError as e:
pr_err("Init failed: " + str(e))
exit(1)
xdg_config_home = os.environ.get('XDG_CONFIG_HOME') or \
os.path.join(os.path.expanduser('~'), '.config')
config_file = os.path.join(xdg_config_home, 'fusesoc', 'fusesoc.conf')
def load_section(config, section_name, file_name=''):
tmp = section_name.split(' ')
_type = tmp[0]
if len(tmp) == 2:
_name = tmp[1]
else:
_name = None
cls = SECTION_MAP.get(_type)
if cls is None:
#Note: The following sections are not in section.py yet
if not section_name in ['plusargs', 'simulator', 'provider']:
pr_warn("Unknown section '{}' in '{}'".format(section_name, file_name))
return None
items = config.get_section(section_name)
section = cls(items)
if section.warnings:
for warning in section.warnings:
pr_warn('Warning: %s in %s' % (warning, file_name))
if _name:
return (section, _name)
else:
return section
config = Config()
# Get the environment variable for further cores
env_cores_root = []
if os.getenv("FUSESOC_CORES"):
env_cores_root = os.getenv("FUSESOC_CORES").split(":")
env_cores_root.reverse()
for cores_root in [config.cores_root,
config.systems_root,
env_cores_root,
args.cores_root]:
try:
cm.add_cores_root(cores_root)
except (RuntimeError, IOError) as e:
pr_warn("Failed to register cores root '{}'".format(str(e)))
# Process global options
if vars(args)['32']:
config.archbits = 32
logger.debug("Forcing 32-bit mode")
elif vars(args)['64']:
config.archbits = 64
logger.debug("Forcing 64-bit mode")
else:
config.archbits = 64 if platform.architecture()[0] == '64bit' else 32
logger.debug("Autodetected " + str(config.archbits) + "-bit mode")
config.monochrome = vars(args)['monochrome']
if config.monochrome:
logger.debug("Monochrome output")
else:
logger.debug("Colorful output")
config.verbose = vars(args)['verbose']
def load_core(self, file):
if os.path.exists(file):
try:
core = Core(file)
self.db.add(core)
except SyntaxError as e:
w = "Failed to parse " + file + ": " + e.msg
pr_warn(w)
logger.warning(w)
except ImportError as e:
pr_warn('Failed to register "{}" due to unknown provider: {}'.format(file, str(e)))
if len(tmp) == 2:
_name = tmp[1]
else:
_name = None
cls = SECTION_MAP.get(_type)
if cls is None:
#Note: The following sections are not in section.py yet
if not section_name in ['plusargs', 'simulator', 'provider']:
pr_warn("Unknown section '{}' in '{}'".format(section_name, file_name))
return None
items = config.get_section(section_name)
section = cls(items)
if section.warnings:
for warning in section.warnings:
pr_warn('Warning: %s in %s' % (warning, file_name))
if _name:
return (section, _name)
else:
return section
f1.write('verilog work ' + src_file.name + '\n')
elif src_file.file_type in ["vhdlSource",
"vhdlSource-87",
"vhdlSource-93"]:
f1.write('vhdl work ' + src_file.logical_name + " " + src_file.name + '\n')
elif src_file.file_type in ['vhdlSource-2008']:
f1.write('vhdl2008 ' + src_file.logical_name + " " + src_file.name + '\n')
elif src_file.file_type in ["systemVerilogSource",
"systemVerilogSource-3.0",
"systemVerilogSource-3.1",
"systemVerilogSource-3.1a",
"verilogSource-2005"]:
f1.write('sv work ' + src_file.name + '\n')
else:
_s = "{} has unknown file type '{}'"
pr_warn(_s.format(src_file.name,
src_file.file_type))
f1.close()
tcl_file = 'xsim.tcl'
f2 = open(os.path.join(self.work_root,tcl_file),'w')
f2.write('add_wave -radix hex /\n')
f2.write('run all\n')
f2.close()
cmd = 'vcom'
args = ['-87']
elif f.file_type == 'vhdlSource-93':
cmd = 'vcom'
args = ['-93']
elif f.file_type == 'vhdlSource-2008':
cmd = 'vcom'
args = ['-2008']
elif f.file_type == 'tclSource':
cmd = None
tcl_main.write("do {}\n".format(f.name))
elif f.file_type == 'user':
cmd = None
else:
_s = "{} has unknown file type '{}'"
pr_warn(_s.format(f.name,
f.file_type))
cmd = None
if cmd:
if not Config().verbose:
args += ['-quiet']
args += ['-work', f.logical_name]
args += [f.name]
tcl_build_rtl.write("{} {}\n".format(cmd, ' '.join(args)))