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if not os.path.isdir(self.files_root):
os.mkdir(self.files_root)
src_files = [self.script_file, self.project_file]
if self.extra_files:
src_files += self.extra_files.split()
for f in src_files:
f_src = os.path.join(self.core_root, f)
f_dst = os.path.join(self.files_root, f)
if(os.path.exists(f_src)):
shutil.copyfile(f_src, f_dst)
else:
pr_err('Cannot find file %s' % f_src)
args = ['-mode', 'batch',
'-source', self.script_file]
Launcher('vivado', args, cwd=self.files_root).run()
def _checkout(self, local_dir):
pr_info("Downloading " + self.repo_name + " from OpenCores")
Launcher('svn', ['co', '-q', '--no-auth-cache',
'-r', self.revision_number,
'--username', 'orpsoc',
'--password', 'orpsoc',
self.repo_path,
local_dir]).run()
def _checkout(self, local_dir):
repo_name = self.config.get('repo_name')
repo_path = REPO_PATH.format(repo_name,
repo_name,
self.config.get('repo_root'))
revision_number = self.config.get('revision')
logger.info("Downloading " + repo_name + " from OpenCores")
if is_mingw():
logger.debug("Using cygpath translation")
local_dir = cygpath(local_dir)
Launcher('svn', ['co', '-q', '--no-auth-cache',
'-r', revision_number,
'--username', 'orpsoc',
'--password', 'orpsoc',
repo_path,
local_dir]).run()
pr_err('VPI modules not supported by Isim: %s' % ', '.join(modules))
#Build simulation model
args = []
args += [ self.toplevel]
args += ['-prj', 'isim.prj']
args += ['-o', 'fusesoc.elf']
for include_dir in self.incdirs:
args += ['-i', include_dir]
for key, value in self.vlogparam.items():
args += ['--generic_top', '{}={}'.format(key, value)]
args += self.isim_options
Launcher('fuse', args,
cwd = self.sim_root,
errormsg = "Failed to compile Isim simulation model").run()
def _checkout(self, local_dir):
#TODO : Sanitize URL
pr_info("Checking out " + self.repo + " to " + local_dir)
args = ['clone', '-q', self.repo, local_dir]
Launcher('git', args).run()
if self.version:
args = ['-C', local_dir, 'checkout', '-q', self.version]
Launcher('git', args).run()
def build(self, args):
super(Ise, self).build(args)
utils.Launcher('xtclsh', [os.path.join(self.work_root, self.system.sanitized_name+'.tcl')],
cwd = self.work_root,
errormsg = "Failed to make FPGA load module").run()
super(Ise, self).done()