How to use the vsg.rule function in vsg

To help you get started, we’ve selected a few vsg examples, based on popular ways it is used in public projects.

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github jeremiah-c-leary / vhdl-style-guide / vsg / rules / function / rule_010.py View on Github external
from vsg import rule
from vsg import utils


class rule_010(rule.rule):
    '''
    General rule 010 checks capitalization consistency of function names.
    '''

    def __init__(self):
        rule.rule.__init__(self, 'function', '010')
        self.fixable = True
        self.solution = 'Inconsistent capitalization of word'
        self.phase = 6
        self.dDatabase = create_database()

    def _analyze(self, oFile, oLine, iLineNumber):
        if oLine.isFunctionKeyword:
            self.dDatabase['function'].append(oLine.line.split()[1])  # TODO: Think if this can be solved in better way.
        if oLine.insideArchitecture:
            if oLine.insideProcess or oLine.insideConcurrent:
github jeremiah-c-leary / vhdl-style-guide / vsg / rules / case / rule_020.py View on Github external
def __init__(self):
        rule.rule.__init__(self, 'case', '020')
        self.phase = 1
        self.solution = 'Remove label after the "end case" keywords'
github jeremiah-c-leary / vhdl-style-guide / vsg / rules / case_item_rule.py View on Github external
from vsg import rule
from vsg import utils
from vsg import parser


class case_item_rule(rule.rule):
    '''
    Checks the case for words.

    Parameters
    ----------

    name : string
       The group the rule belongs to.

    identifier : string
       unique identifier.  Usually in the form of 00N.

    trigger : parser object type
       object type to apply the case check against
    '''
github jeremiah-c-leary / vhdl-style-guide / vsg / rules / case / rule_001.py View on Github external
from vsg import rule
from vsg import check
from vsg import fix
from vsg import utils


class rule_001(rule.rule):
    '''Case rule 001 checks for the proper indentation at the beginning of the line.'''

    def __init__(self):
        rule.rule.__init__(self, 'case', '001')
        self.solution = 'Ensure proper indentation.'
        self.phase = 4

    def _analyze(self, oFile, oLine, iLineNumber):
        if oLine.isCaseKeyword or oLine.isCaseWhenKeyword or oLine.isEndCaseKeyword:
            check.indent(self, oLine, iLineNumber)

    def _fix_violations(self, oFile):
        for dViolation in self.violations:
            fix.indent(self, utils.get_violating_line(oFile, dViolation))
github jeremiah-c-leary / vhdl-style-guide / vsg / rules / function.py View on Github external
def __init__(self):
        rule.rule.__init__(self)
        self.name = 'function'
github jeremiah-c-leary / vhdl-style-guide / vsg / rules / architecture / rule_022.py View on Github external
from vsg import rule
from vsg import check
from vsg import fix
from vsg import utils

import re


class rule_022(rule.rule):
    '''
    Architecture rule 022 checks for a single space after the "end architecture" keywords and the architecture name.
    '''

    def __init__(self):
        rule.rule.__init__(self, 'architecture', '022')
        self.solution = 'Ensure a single space exists between "architecture" and the architecture name.'
        self.phase = 2

    def _analyze(self, oFile, oLine, iLineNumber):
        if oLine.isEndArchitecture and re.match('^\s*end\s+architecture\s+\w', oLine.lineLower):
            check.is_single_space_after(self, 'architecture', oLine, iLineNumber)

    def _fix_violations(self, oFile):
        for dViolation in self.violations:
            fix.enforce_one_space_after_word(self, utils.get_violating_line(oFile, dViolation), 'architecture')
github jeremiah-c-leary / vhdl-style-guide / vsg / rules / process / rule_030.py View on Github external
from vsg import rule
from vsg import utils

import re


class rule_030(rule.rule):
    '''
    Process rule 030 checks for single signal declarations on sensitivity list lines.
    '''

    def __init__(self):
        rule.rule.__init__(self)
        self.name = 'process'
        self.identifier = '030'
        self.solution = 'Compact sensitivity list to reduce the number of lines it uses.'
        self.phase = 1
        self.fixable = False

    def _pre_analyze(self):
        self.iCount = 0
        self.sSensitivityList = ''
github jeremiah-c-leary / vhdl-style-guide / vsg / rules / process / rule_018.py View on Github external
from vsg import rule
from vsg import utils

import re


class rule_018(rule.rule):
    '''
    Process rule 018 checks the "end process" has a label.
    '''

    def __init__(self):
        rule.rule.__init__(self, 'process', '018')
        self.solution = 'Add a label for the "end process".'
        self.phase = 1
        self.subphase = 2

    def _pre_analyze(self):
        self.previousLabel = ''
        self.fProcessHadBeginLabel = False

    def _analyze(self, oFile, oLine, iLineNumber):
        if oLine.isProcessKeyword:
github jeremiah-c-leary / vhdl-style-guide / vsg / rules / type_definition / rule_008.py View on Github external
def __init__(self):
        rule.rule.__init__(self, 'type', '008')
        self.solution = 'Move the closing parenthesis to it\'s own line.'
        self.phase = 1