How to use the unicorn.mips_const function in unicorn
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'CPR0_0': csts.UC_MIPS_REG_0, 'CPR0_1': csts.UC_MIPS_REG_1,
'CPR0_10': csts.UC_MIPS_REG_10, 'CPR0_11': csts.UC_MIPS_REG_11,
'CPR0_12': csts.UC_MIPS_REG_12, 'CPR0_13': csts.UC_MIPS_REG_13,
'CPR0_14': csts.UC_MIPS_REG_14, 'CPR0_15': csts.UC_MIPS_REG_15,
'CPR0_16': csts.UC_MIPS_REG_16, 'CPR0_17': csts.UC_MIPS_REG_17,
'CPR0_18': csts.UC_MIPS_REG_18, 'CPR0_19': csts.UC_MIPS_REG_19,
'CPR0_2': csts.UC_MIPS_REG_2, 'CPR0_20': csts.UC_MIPS_REG_20,
'CPR0_21': csts.UC_MIPS_REG_21, 'CPR0_22': csts.UC_MIPS_REG_22,
'CPR0_23': csts.UC_MIPS_REG_23, 'CPR0_24': csts.UC_MIPS_REG_24,
'CPR0_25': csts.UC_MIPS_REG_25, 'CPR0_26': csts.UC_MIPS_REG_26,
'CPR0_27': csts.UC_MIPS_REG_27, 'CPR0_28': csts.UC_MIPS_REG_28,
'CPR0_29': csts.UC_MIPS_REG_29, 'CPR0_3': csts.UC_MIPS_REG_3,
'CPR0_30': csts.UC_MIPS_REG_30, 'CPR0_31': csts.UC_MIPS_REG_31,
'CPR0_4': csts.UC_MIPS_REG_4, 'CPR0_5': csts.UC_MIPS_REG_5,
'CPR0_6': csts.UC_MIPS_REG_6, 'CPR0_7': csts.UC_MIPS_REG_7,
'CPR0_8': csts.UC_MIPS_REG_8, 'CPR0_9': csts.UC_MIPS_REG_9,
'A0': csts.UC_MIPS_REG_A0, 'A1': csts.UC_MIPS_REG_A1,
'A2': csts.UC_MIPS_REG_A2, 'CC1': csts.UC_MIPS_REG_CC1,
'A3': csts.UC_MIPS_REG_A3, 'CC0': csts.UC_MIPS_REG_CC0,
'CC2': csts.UC_MIPS_REG_CC2, 'CC3': csts.UC_MIPS_REG_CC3,
'CC4': csts.UC_MIPS_REG_CC4, 'CC5': csts.UC_MIPS_REG_CC5,
'CC6': csts.UC_MIPS_REG_CC6, 'CC7': csts.UC_MIPS_REG_CC7,
'F0': csts.UC_MIPS_REG_F0, 'F1': csts.UC_MIPS_REG_F1,
'F10': csts.UC_MIPS_REG_F10, 'F5': csts.UC_MIPS_REG_F5,
'F11': csts.UC_MIPS_REG_F11, 'F12': csts.UC_MIPS_REG_F12,
'F13': csts.UC_MIPS_REG_F13, 'F14': csts.UC_MIPS_REG_F14,
'F15': csts.UC_MIPS_REG_F15, 'F16': csts.UC_MIPS_REG_F16,
'F17': csts.UC_MIPS_REG_F17, 'F18': csts.UC_MIPS_REG_F18,
'F19': csts.UC_MIPS_REG_F19, 'F2': csts.UC_MIPS_REG_F2,
'F20': csts.UC_MIPS_REG_F20, 'F21': csts.UC_MIPS_REG_F21,
'F22': csts.UC_MIPS_REG_F22, 'F23': csts.UC_MIPS_REG_F23,
'F24': csts.UC_MIPS_REG_F24, 'F25': csts.UC_MIPS_REG_F25,'T2': csts.UC_MIPS_REG_T2, 'T3': csts.UC_MIPS_REG_T3,
'T4': csts.UC_MIPS_REG_T4, 'T5': csts.UC_MIPS_REG_T5,
'T6': csts.UC_MIPS_REG_T6, 'T7': csts.UC_MIPS_REG_T7,
'T8': csts.UC_MIPS_REG_T8, 'T9': csts.UC_MIPS_REG_T9,
'V0': csts.UC_MIPS_REG_V0, 'V1': csts.UC_MIPS_REG_V1,
'W0': csts.UC_MIPS_REG_W0, 'W1': csts.UC_MIPS_REG_W1,
'W10': csts.UC_MIPS_REG_W10, 'W11': csts.UC_MIPS_REG_W11,
'W12': csts.UC_MIPS_REG_W12, 'W13': csts.UC_MIPS_REG_W13,
'W14': csts.UC_MIPS_REG_W14, 'W15': csts.UC_MIPS_REG_W15,
'W16': csts.UC_MIPS_REG_W16, 'W17': csts.UC_MIPS_REG_W17,
'W18': csts.UC_MIPS_REG_W18, 'W19': csts.UC_MIPS_REG_W19,
'W2': csts.UC_MIPS_REG_W2, 'W20': csts.UC_MIPS_REG_W20,
'W21': csts.UC_MIPS_REG_W21, 'W22': csts.UC_MIPS_REG_W22,
'W23': csts.UC_MIPS_REG_W23, 'W24': csts.UC_MIPS_REG_W24,
'W25': csts.UC_MIPS_REG_W25, 'W26': csts.UC_MIPS_REG_W26,
'W27': csts.UC_MIPS_REG_W27, 'W28': csts.UC_MIPS_REG_W28,
'W29': csts.UC_MIPS_REG_W29, 'W3': csts.UC_MIPS_REG_W3,
'W30': csts.UC_MIPS_REG_W30, 'W31': csts.UC_MIPS_REG_W31,
'W4': csts.UC_MIPS_REG_W4, 'W5': csts.UC_MIPS_REG_W5,
'W6': csts.UC_MIPS_REG_W6, 'W7': csts.UC_MIPS_REG_W7,
'W8': csts.UC_MIPS_REG_W8, 'W9': csts.UC_MIPS_REG_W9,
}
self.pc_reg_name = "PC"
self.pc_reg_value = csts.UC_MIPS_REG_PC
super(UcWrapCPU_mips32l, self).__init__(*args, **kwargs)def __init__(self, *args, **kwargs):
import unicorn.mips_const as csts
self.regs = {
'CPR0_0': csts.UC_MIPS_REG_0, 'CPR0_1': csts.UC_MIPS_REG_1,
'CPR0_10': csts.UC_MIPS_REG_10, 'CPR0_11': csts.UC_MIPS_REG_11,
'CPR0_12': csts.UC_MIPS_REG_12, 'CPR0_13': csts.UC_MIPS_REG_13,
'CPR0_14': csts.UC_MIPS_REG_14, 'CPR0_15': csts.UC_MIPS_REG_15,
'CPR0_16': csts.UC_MIPS_REG_16, 'CPR0_17': csts.UC_MIPS_REG_17,
'CPR0_18': csts.UC_MIPS_REG_18, 'CPR0_19': csts.UC_MIPS_REG_19,
'CPR0_2': csts.UC_MIPS_REG_2, 'CPR0_20': csts.UC_MIPS_REG_20,
'CPR0_21': csts.UC_MIPS_REG_21, 'CPR0_22': csts.UC_MIPS_REG_22,
'CPR0_23': csts.UC_MIPS_REG_23, 'CPR0_24': csts.UC_MIPS_REG_24,
'CPR0_25': csts.UC_MIPS_REG_25, 'CPR0_26': csts.UC_MIPS_REG_26,
'CPR0_27': csts.UC_MIPS_REG_27, 'CPR0_28': csts.UC_MIPS_REG_28,
'CPR0_29': csts.UC_MIPS_REG_29, 'CPR0_3': csts.UC_MIPS_REG_3,
'CPR0_30': csts.UC_MIPS_REG_30, 'CPR0_31': csts.UC_MIPS_REG_31,
'CPR0_4': csts.UC_MIPS_REG_4, 'CPR0_5': csts.UC_MIPS_REG_5,
'CPR0_6': csts.UC_MIPS_REG_6, 'CPR0_7': csts.UC_MIPS_REG_7,
'CPR0_8': csts.UC_MIPS_REG_8, 'CPR0_9': csts.UC_MIPS_REG_9,
'A0': csts.UC_MIPS_REG_A0, 'A1': csts.UC_MIPS_REG_A1,
'A2': csts.UC_MIPS_REG_A2, 'CC1': csts.UC_MIPS_REG_CC1,
'A3': csts.UC_MIPS_REG_A3, 'CC0': csts.UC_MIPS_REG_CC0,
'CC2': csts.UC_MIPS_REG_CC2, 'CC3': csts.UC_MIPS_REG_CC3,
'CC4': csts.UC_MIPS_REG_CC4, 'CC5': csts.UC_MIPS_REG_CC5,
'CC6': csts.UC_MIPS_REG_CC6, 'CC7': csts.UC_MIPS_REG_CC7,
'F0': csts.UC_MIPS_REG_F0, 'F1': csts.UC_MIPS_REG_F1,
'F10': csts.UC_MIPS_REG_F10, 'F5': csts.UC_MIPS_REG_F5,'F28': csts.UC_MIPS_REG_F28, 'F29': csts.UC_MIPS_REG_F29,
'F3': csts.UC_MIPS_REG_F3, 'F30': csts.UC_MIPS_REG_F30,
'F31': csts.UC_MIPS_REG_F31, 'F4': csts.UC_MIPS_REG_F4,
'F6': csts.UC_MIPS_REG_F6, 'F7': csts.UC_MIPS_REG_F7,
'F8': csts.UC_MIPS_REG_F8,
'F9': csts.UC_MIPS_REG_F9, 'FCC0': csts.UC_MIPS_REG_FCC0,
'FCC1': csts.UC_MIPS_REG_FCC1, 'FCC2': csts.UC_MIPS_REG_FCC2,
'FCC3': csts.UC_MIPS_REG_FCC3, 'FCC4': csts.UC_MIPS_REG_FCC4,
'FCC5': csts.UC_MIPS_REG_FCC5, 'FCC6': csts.UC_MIPS_REG_FCC6,
'FCC7': csts.UC_MIPS_REG_FCC7, 'FP': csts.UC_MIPS_REG_FP,
'GP': csts.UC_MIPS_REG_GP, 'R_HI': csts.UC_MIPS_REG_HI,
'K0': csts.UC_MIPS_REG_K0, 'RA': csts.UC_MIPS_REG_RA,
'K1': csts.UC_MIPS_REG_K1, 'R_LO': csts.UC_MIPS_REG_LO,
'S0': csts.UC_MIPS_REG_S0, 'S1': csts.UC_MIPS_REG_S1,
'S2': csts.UC_MIPS_REG_S2, 'S3': csts.UC_MIPS_REG_S3,
'S4': csts.UC_MIPS_REG_S4, 'S5': csts.UC_MIPS_REG_S5,
'S6': csts.UC_MIPS_REG_S6, 'S7': csts.UC_MIPS_REG_S7,
'S8': csts.UC_MIPS_REG_S8, 'SP': csts.UC_MIPS_REG_SP,
'T0': csts.UC_MIPS_REG_T0, 'T1': csts.UC_MIPS_REG_T1,
'T2': csts.UC_MIPS_REG_T2, 'T3': csts.UC_MIPS_REG_T3,
'T4': csts.UC_MIPS_REG_T4, 'T5': csts.UC_MIPS_REG_T5,
'T6': csts.UC_MIPS_REG_T6, 'T7': csts.UC_MIPS_REG_T7,
'T8': csts.UC_MIPS_REG_T8, 'T9': csts.UC_MIPS_REG_T9,
'V0': csts.UC_MIPS_REG_V0, 'V1': csts.UC_MIPS_REG_V1,
'W0': csts.UC_MIPS_REG_W0, 'W1': csts.UC_MIPS_REG_W1,
'W10': csts.UC_MIPS_REG_W10, 'W11': csts.UC_MIPS_REG_W11,
'W12': csts.UC_MIPS_REG_W12, 'W13': csts.UC_MIPS_REG_W13,
'W14': csts.UC_MIPS_REG_W14, 'W15': csts.UC_MIPS_REG_W15,
'W16': csts.UC_MIPS_REG_W16, 'W17': csts.UC_MIPS_REG_W17,
'W18': csts.UC_MIPS_REG_W18, 'W19': csts.UC_MIPS_REG_W19,
'W2': csts.UC_MIPS_REG_W2, 'W20': csts.UC_MIPS_REG_W20,
'W21': csts.UC_MIPS_REG_W21, 'W22': csts.UC_MIPS_REG_W22,'CPR0_6': csts.UC_MIPS_REG_6, 'CPR0_7': csts.UC_MIPS_REG_7,
'CPR0_8': csts.UC_MIPS_REG_8, 'CPR0_9': csts.UC_MIPS_REG_9,
'A0': csts.UC_MIPS_REG_A0, 'A1': csts.UC_MIPS_REG_A1,
'A2': csts.UC_MIPS_REG_A2, 'CC1': csts.UC_MIPS_REG_CC1,
'A3': csts.UC_MIPS_REG_A3, 'CC0': csts.UC_MIPS_REG_CC0,
'CC2': csts.UC_MIPS_REG_CC2, 'CC3': csts.UC_MIPS_REG_CC3,
'CC4': csts.UC_MIPS_REG_CC4, 'CC5': csts.UC_MIPS_REG_CC5,
'CC6': csts.UC_MIPS_REG_CC6, 'CC7': csts.UC_MIPS_REG_CC7,
'F0': csts.UC_MIPS_REG_F0, 'F1': csts.UC_MIPS_REG_F1,
'F10': csts.UC_MIPS_REG_F10, 'F5': csts.UC_MIPS_REG_F5,
'F11': csts.UC_MIPS_REG_F11, 'F12': csts.UC_MIPS_REG_F12,
'F13': csts.UC_MIPS_REG_F13, 'F14': csts.UC_MIPS_REG_F14,
'F15': csts.UC_MIPS_REG_F15, 'F16': csts.UC_MIPS_REG_F16,
'F17': csts.UC_MIPS_REG_F17, 'F18': csts.UC_MIPS_REG_F18,
'F19': csts.UC_MIPS_REG_F19, 'F2': csts.UC_MIPS_REG_F2,
'F20': csts.UC_MIPS_REG_F20, 'F21': csts.UC_MIPS_REG_F21,
'F22': csts.UC_MIPS_REG_F22, 'F23': csts.UC_MIPS_REG_F23,
'F24': csts.UC_MIPS_REG_F24, 'F25': csts.UC_MIPS_REG_F25,
'F26': csts.UC_MIPS_REG_F26, 'F27': csts.UC_MIPS_REG_F27,
'F28': csts.UC_MIPS_REG_F28, 'F29': csts.UC_MIPS_REG_F29,
'F3': csts.UC_MIPS_REG_F3, 'F30': csts.UC_MIPS_REG_F30,
'F31': csts.UC_MIPS_REG_F31, 'F4': csts.UC_MIPS_REG_F4,
'F6': csts.UC_MIPS_REG_F6, 'F7': csts.UC_MIPS_REG_F7,
'F8': csts.UC_MIPS_REG_F8,
'F9': csts.UC_MIPS_REG_F9, 'FCC0': csts.UC_MIPS_REG_FCC0,
'FCC1': csts.UC_MIPS_REG_FCC1, 'FCC2': csts.UC_MIPS_REG_FCC2,
'FCC3': csts.UC_MIPS_REG_FCC3, 'FCC4': csts.UC_MIPS_REG_FCC4,
'FCC5': csts.UC_MIPS_REG_FCC5, 'FCC6': csts.UC_MIPS_REG_FCC6,
'FCC7': csts.UC_MIPS_REG_FCC7, 'FP': csts.UC_MIPS_REG_FP,
'GP': csts.UC_MIPS_REG_GP, 'R_HI': csts.UC_MIPS_REG_HI,
'K0': csts.UC_MIPS_REG_K0, 'RA': csts.UC_MIPS_REG_RA,
'K1': csts.UC_MIPS_REG_K1, 'R_LO': csts.UC_MIPS_REG_LO,'CPR0_30': csts.UC_MIPS_REG_30, 'CPR0_31': csts.UC_MIPS_REG_31,
'CPR0_4': csts.UC_MIPS_REG_4, 'CPR0_5': csts.UC_MIPS_REG_5,
'CPR0_6': csts.UC_MIPS_REG_6, 'CPR0_7': csts.UC_MIPS_REG_7,
'CPR0_8': csts.UC_MIPS_REG_8, 'CPR0_9': csts.UC_MIPS_REG_9,
'A0': csts.UC_MIPS_REG_A0, 'A1': csts.UC_MIPS_REG_A1,
'A2': csts.UC_MIPS_REG_A2, 'CC1': csts.UC_MIPS_REG_CC1,
'A3': csts.UC_MIPS_REG_A3, 'CC0': csts.UC_MIPS_REG_CC0,
'CC2': csts.UC_MIPS_REG_CC2, 'CC3': csts.UC_MIPS_REG_CC3,
'CC4': csts.UC_MIPS_REG_CC4, 'CC5': csts.UC_MIPS_REG_CC5,
'CC6': csts.UC_MIPS_REG_CC6, 'CC7': csts.UC_MIPS_REG_CC7,
'F0': csts.UC_MIPS_REG_F0, 'F1': csts.UC_MIPS_REG_F1,
'F10': csts.UC_MIPS_REG_F10, 'F5': csts.UC_MIPS_REG_F5,
'F11': csts.UC_MIPS_REG_F11, 'F12': csts.UC_MIPS_REG_F12,
'F13': csts.UC_MIPS_REG_F13, 'F14': csts.UC_MIPS_REG_F14,
'F15': csts.UC_MIPS_REG_F15, 'F16': csts.UC_MIPS_REG_F16,
'F17': csts.UC_MIPS_REG_F17, 'F18': csts.UC_MIPS_REG_F18,
'F19': csts.UC_MIPS_REG_F19, 'F2': csts.UC_MIPS_REG_F2,
'F20': csts.UC_MIPS_REG_F20, 'F21': csts.UC_MIPS_REG_F21,
'F22': csts.UC_MIPS_REG_F22, 'F23': csts.UC_MIPS_REG_F23,
'F24': csts.UC_MIPS_REG_F24, 'F25': csts.UC_MIPS_REG_F25,
'F26': csts.UC_MIPS_REG_F26, 'F27': csts.UC_MIPS_REG_F27,
'F28': csts.UC_MIPS_REG_F28, 'F29': csts.UC_MIPS_REG_F29,
'F3': csts.UC_MIPS_REG_F3, 'F30': csts.UC_MIPS_REG_F30,
'F31': csts.UC_MIPS_REG_F31, 'F4': csts.UC_MIPS_REG_F4,
'F6': csts.UC_MIPS_REG_F6, 'F7': csts.UC_MIPS_REG_F7,
'F8': csts.UC_MIPS_REG_F8,
'F9': csts.UC_MIPS_REG_F9, 'FCC0': csts.UC_MIPS_REG_FCC0,
'FCC1': csts.UC_MIPS_REG_FCC1, 'FCC2': csts.UC_MIPS_REG_FCC2,
'FCC3': csts.UC_MIPS_REG_FCC3, 'FCC4': csts.UC_MIPS_REG_FCC4,
'FCC5': csts.UC_MIPS_REG_FCC5, 'FCC6': csts.UC_MIPS_REG_FCC6,
'FCC7': csts.UC_MIPS_REG_FCC7, 'FP': csts.UC_MIPS_REG_FP,
'GP': csts.UC_MIPS_REG_GP, 'R_HI': csts.UC_MIPS_REG_HI,'S8': csts.UC_MIPS_REG_S8, 'SP': csts.UC_MIPS_REG_SP,
'T0': csts.UC_MIPS_REG_T0, 'T1': csts.UC_MIPS_REG_T1,
'T2': csts.UC_MIPS_REG_T2, 'T3': csts.UC_MIPS_REG_T3,
'T4': csts.UC_MIPS_REG_T4, 'T5': csts.UC_MIPS_REG_T5,
'T6': csts.UC_MIPS_REG_T6, 'T7': csts.UC_MIPS_REG_T7,
'T8': csts.UC_MIPS_REG_T8, 'T9': csts.UC_MIPS_REG_T9,
'V0': csts.UC_MIPS_REG_V0, 'V1': csts.UC_MIPS_REG_V1,
'W0': csts.UC_MIPS_REG_W0, 'W1': csts.UC_MIPS_REG_W1,
'W10': csts.UC_MIPS_REG_W10, 'W11': csts.UC_MIPS_REG_W11,
'W12': csts.UC_MIPS_REG_W12, 'W13': csts.UC_MIPS_REG_W13,
'W14': csts.UC_MIPS_REG_W14, 'W15': csts.UC_MIPS_REG_W15,
'W16': csts.UC_MIPS_REG_W16, 'W17': csts.UC_MIPS_REG_W17,
'W18': csts.UC_MIPS_REG_W18, 'W19': csts.UC_MIPS_REG_W19,
'W2': csts.UC_MIPS_REG_W2, 'W20': csts.UC_MIPS_REG_W20,
'W21': csts.UC_MIPS_REG_W21, 'W22': csts.UC_MIPS_REG_W22,
'W23': csts.UC_MIPS_REG_W23, 'W24': csts.UC_MIPS_REG_W24,
'W25': csts.UC_MIPS_REG_W25, 'W26': csts.UC_MIPS_REG_W26,
'W27': csts.UC_MIPS_REG_W27, 'W28': csts.UC_MIPS_REG_W28,
'W29': csts.UC_MIPS_REG_W29, 'W3': csts.UC_MIPS_REG_W3,
'W30': csts.UC_MIPS_REG_W30, 'W31': csts.UC_MIPS_REG_W31,
'W4': csts.UC_MIPS_REG_W4, 'W5': csts.UC_MIPS_REG_W5,
'W6': csts.UC_MIPS_REG_W6, 'W7': csts.UC_MIPS_REG_W7,
'W8': csts.UC_MIPS_REG_W8, 'W9': csts.UC_MIPS_REG_W9,
}
self.pc_reg_name = "PC"
self.pc_reg_value = csts.UC_MIPS_REG_PC
super(UcWrapCPU_mips32l, self).__init__(*args, **kwargs)'F9': csts.UC_MIPS_REG_F9, 'FCC0': csts.UC_MIPS_REG_FCC0,
'FCC1': csts.UC_MIPS_REG_FCC1, 'FCC2': csts.UC_MIPS_REG_FCC2,
'FCC3': csts.UC_MIPS_REG_FCC3, 'FCC4': csts.UC_MIPS_REG_FCC4,
'FCC5': csts.UC_MIPS_REG_FCC5, 'FCC6': csts.UC_MIPS_REG_FCC6,
'FCC7': csts.UC_MIPS_REG_FCC7, 'FP': csts.UC_MIPS_REG_FP,
'GP': csts.UC_MIPS_REG_GP, 'R_HI': csts.UC_MIPS_REG_HI,
'K0': csts.UC_MIPS_REG_K0, 'RA': csts.UC_MIPS_REG_RA,
'K1': csts.UC_MIPS_REG_K1, 'R_LO': csts.UC_MIPS_REG_LO,
'S0': csts.UC_MIPS_REG_S0, 'S1': csts.UC_MIPS_REG_S1,
'S2': csts.UC_MIPS_REG_S2, 'S3': csts.UC_MIPS_REG_S3,
'S4': csts.UC_MIPS_REG_S4, 'S5': csts.UC_MIPS_REG_S5,
'S6': csts.UC_MIPS_REG_S6, 'S7': csts.UC_MIPS_REG_S7,
'S8': csts.UC_MIPS_REG_S8, 'SP': csts.UC_MIPS_REG_SP,
'T0': csts.UC_MIPS_REG_T0, 'T1': csts.UC_MIPS_REG_T1,
'T2': csts.UC_MIPS_REG_T2, 'T3': csts.UC_MIPS_REG_T3,
'T4': csts.UC_MIPS_REG_T4, 'T5': csts.UC_MIPS_REG_T5,
'T6': csts.UC_MIPS_REG_T6, 'T7': csts.UC_MIPS_REG_T7,
'T8': csts.UC_MIPS_REG_T8, 'T9': csts.UC_MIPS_REG_T9,
'V0': csts.UC_MIPS_REG_V0, 'V1': csts.UC_MIPS_REG_V1,
'W0': csts.UC_MIPS_REG_W0, 'W1': csts.UC_MIPS_REG_W1,
'W10': csts.UC_MIPS_REG_W10, 'W11': csts.UC_MIPS_REG_W11,
'W12': csts.UC_MIPS_REG_W12, 'W13': csts.UC_MIPS_REG_W13,
'W14': csts.UC_MIPS_REG_W14, 'W15': csts.UC_MIPS_REG_W15,
'W16': csts.UC_MIPS_REG_W16, 'W17': csts.UC_MIPS_REG_W17,
'W18': csts.UC_MIPS_REG_W18, 'W19': csts.UC_MIPS_REG_W19,
'W2': csts.UC_MIPS_REG_W2, 'W20': csts.UC_MIPS_REG_W20,
'W21': csts.UC_MIPS_REG_W21, 'W22': csts.UC_MIPS_REG_W22,
'W23': csts.UC_MIPS_REG_W23, 'W24': csts.UC_MIPS_REG_W24,
'W25': csts.UC_MIPS_REG_W25, 'W26': csts.UC_MIPS_REG_W26,
'W27': csts.UC_MIPS_REG_W27, 'W28': csts.UC_MIPS_REG_W28,
'W29': csts.UC_MIPS_REG_W29, 'W3': csts.UC_MIPS_REG_W3,
'W30': csts.UC_MIPS_REG_W30, 'W31': csts.UC_MIPS_REG_W31,'CPR0_12': csts.UC_MIPS_REG_12, 'CPR0_13': csts.UC_MIPS_REG_13,
'CPR0_14': csts.UC_MIPS_REG_14, 'CPR0_15': csts.UC_MIPS_REG_15,
'CPR0_16': csts.UC_MIPS_REG_16, 'CPR0_17': csts.UC_MIPS_REG_17,
'CPR0_18': csts.UC_MIPS_REG_18, 'CPR0_19': csts.UC_MIPS_REG_19,
'CPR0_2': csts.UC_MIPS_REG_2, 'CPR0_20': csts.UC_MIPS_REG_20,
'CPR0_21': csts.UC_MIPS_REG_21, 'CPR0_22': csts.UC_MIPS_REG_22,
'CPR0_23': csts.UC_MIPS_REG_23, 'CPR0_24': csts.UC_MIPS_REG_24,
'CPR0_25': csts.UC_MIPS_REG_25, 'CPR0_26': csts.UC_MIPS_REG_26,
'CPR0_27': csts.UC_MIPS_REG_27, 'CPR0_28': csts.UC_MIPS_REG_28,
'CPR0_29': csts.UC_MIPS_REG_29, 'CPR0_3': csts.UC_MIPS_REG_3,
'CPR0_30': csts.UC_MIPS_REG_30, 'CPR0_31': csts.UC_MIPS_REG_31,
'CPR0_4': csts.UC_MIPS_REG_4, 'CPR0_5': csts.UC_MIPS_REG_5,
'CPR0_6': csts.UC_MIPS_REG_6, 'CPR0_7': csts.UC_MIPS_REG_7,
'CPR0_8': csts.UC_MIPS_REG_8, 'CPR0_9': csts.UC_MIPS_REG_9,
'A0': csts.UC_MIPS_REG_A0, 'A1': csts.UC_MIPS_REG_A1,
'A2': csts.UC_MIPS_REG_A2, 'CC1': csts.UC_MIPS_REG_CC1,
'A3': csts.UC_MIPS_REG_A3, 'CC0': csts.UC_MIPS_REG_CC0,
'CC2': csts.UC_MIPS_REG_CC2, 'CC3': csts.UC_MIPS_REG_CC3,
'CC4': csts.UC_MIPS_REG_CC4, 'CC5': csts.UC_MIPS_REG_CC5,
'CC6': csts.UC_MIPS_REG_CC6, 'CC7': csts.UC_MIPS_REG_CC7,
'F0': csts.UC_MIPS_REG_F0, 'F1': csts.UC_MIPS_REG_F1,
'F10': csts.UC_MIPS_REG_F10, 'F5': csts.UC_MIPS_REG_F5,
'F11': csts.UC_MIPS_REG_F11, 'F12': csts.UC_MIPS_REG_F12,
'F13': csts.UC_MIPS_REG_F13, 'F14': csts.UC_MIPS_REG_F14,
'F15': csts.UC_MIPS_REG_F15, 'F16': csts.UC_MIPS_REG_F16,
'F17': csts.UC_MIPS_REG_F17, 'F18': csts.UC_MIPS_REG_F18,
'F19': csts.UC_MIPS_REG_F19, 'F2': csts.UC_MIPS_REG_F2,
'F20': csts.UC_MIPS_REG_F20, 'F21': csts.UC_MIPS_REG_F21,
'F22': csts.UC_MIPS_REG_F22, 'F23': csts.UC_MIPS_REG_F23,
'F24': csts.UC_MIPS_REG_F24, 'F25': csts.UC_MIPS_REG_F25,
'F26': csts.UC_MIPS_REG_F26, 'F27': csts.UC_MIPS_REG_F27,
'F28': csts.UC_MIPS_REG_F28, 'F29': csts.UC_MIPS_REG_F29,'T4': csts.UC_MIPS_REG_T4, 'T5': csts.UC_MIPS_REG_T5,
'T6': csts.UC_MIPS_REG_T6, 'T7': csts.UC_MIPS_REG_T7,
'T8': csts.UC_MIPS_REG_T8, 'T9': csts.UC_MIPS_REG_T9,
'V0': csts.UC_MIPS_REG_V0, 'V1': csts.UC_MIPS_REG_V1,
'W0': csts.UC_MIPS_REG_W0, 'W1': csts.UC_MIPS_REG_W1,
'W10': csts.UC_MIPS_REG_W10, 'W11': csts.UC_MIPS_REG_W11,
'W12': csts.UC_MIPS_REG_W12, 'W13': csts.UC_MIPS_REG_W13,
'W14': csts.UC_MIPS_REG_W14, 'W15': csts.UC_MIPS_REG_W15,
'W16': csts.UC_MIPS_REG_W16, 'W17': csts.UC_MIPS_REG_W17,
'W18': csts.UC_MIPS_REG_W18, 'W19': csts.UC_MIPS_REG_W19,
'W2': csts.UC_MIPS_REG_W2, 'W20': csts.UC_MIPS_REG_W20,
'W21': csts.UC_MIPS_REG_W21, 'W22': csts.UC_MIPS_REG_W22,
'W23': csts.UC_MIPS_REG_W23, 'W24': csts.UC_MIPS_REG_W24,
'W25': csts.UC_MIPS_REG_W25, 'W26': csts.UC_MIPS_REG_W26,
'W27': csts.UC_MIPS_REG_W27, 'W28': csts.UC_MIPS_REG_W28,
'W29': csts.UC_MIPS_REG_W29, 'W3': csts.UC_MIPS_REG_W3,
'W30': csts.UC_MIPS_REG_W30, 'W31': csts.UC_MIPS_REG_W31,
'W4': csts.UC_MIPS_REG_W4, 'W5': csts.UC_MIPS_REG_W5,
'W6': csts.UC_MIPS_REG_W6, 'W7': csts.UC_MIPS_REG_W7,
'W8': csts.UC_MIPS_REG_W8, 'W9': csts.UC_MIPS_REG_W9,
}
self.pc_reg_name = "PC"
self.pc_reg_value = csts.UC_MIPS_REG_PC
super(UcWrapCPU_mips32l, self).__init__(*args, **kwargs)
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