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# Create the part with the part definition.
part = _mk_subckt_part(line) # Create un-filled part template.
# Flesh-out the part.
part.filename = filepath # Store filename where this part came from.
# Parse the part definition.
pieces = part.part_defn.split()
try:
# part defn: .subckt part_name pin1, pin2, ... pinN.
part.name = pieces[1]
part.pins = [Pin(num=p, name=p) for p in pieces[2:]]
part.associate_pins()
except IndexError:
logger.warn("Misformatted SPICE subcircuit: {}".format(part.part_defn))
else:
# Now find a symbol file for the part to assign names to the pins.
# First, check for LTSpice symbol file.
sym_file, _ = find_and_open_file(
part.name,
lib_search_paths_,
".asy",
allow_failure=True,
exclude_binary=True,
descend=-1,
)
if sym_file:
pin_names = []
pin_indices = []
for sym_line in sym_file:
if sym_line.lower().startswith("pinattr pinname"):
filename=filename,
paths=subdirs,
ext=ext,
allow_failure=True,
exclude_binary=exclude_binary,
descend=descend - 1,
)
if fp:
return fp, fn
# Couldn't find the file.
if allow_failure:
return None, None
else:
log_and_raise(
logger, FileNotFoundError, "Can't open file: {}.\n".format(filename)
)
def __iadd__(self, *nets_pins_buses):
nets_pins = []
for item in expand_buses(flatten(nets_pins_buses)):
if isinstance(item, (Pin, Net, ProtoNet)):
nets_pins.append(item)
else:
log_and_raise(
logger,
ValueError,
"Can't make connections to a {} ({}).".format(
type(item), item.__name__
),
)
if len(nets_pins) != len(self):
if Net in [type(item) for item in self] or len(nets_pins) > 1:
log_and_raise(
logger,
ValueError,
"Connection mismatch {} != {}!".format(len(self), len(nets_pins)),
)
# If just a single net is to be connected, make a list out of it that's
# just as long as the list of pins to connect to. This will connect
for k, v in list(attribs.items()):
if isinstance(v, (list, tuple)):
num_copies.add(len(v))
else:
num_copies.add(1)
num_copies = list(num_copies)
if len(num_copies) > 2:
log_and_raise(
logger,
ValueError,
"Mismatched lengths of attributes: {}!".format(num_copies),
)
elif len(num_copies) > 1 and min(num_copies) > 1:
log_and_raise(
logger,
ValueError,
"Mismatched lengths of attributes: {}!".format(num_copies),
)
try:
return max(num_copies)
except ValueError:
return 0 # If the list if empty.
try:
value = self.value
if not value:
value = self.name
except AttributeError:
try:
value = self.name
except AttributeError:
value = self.ref_prefix
value = add_quotes(value)
try:
footprint = self.footprint
except AttributeError:
logger.error("No footprint for {part}/{ref}.".format(part=self.name, ref=ref))
footprint = "No Footprint"
footprint = add_quotes(footprint)
lib = add_quotes(getattr(self, "lib", "NO_LIB")) # pylint: disable=unused-variable
name = add_quotes(self.name) # pylint: disable=unused-variable
# Embed the hierarchy along with a random integer into the sheetpath for each component.
# This enables hierarchical selection in pcbnew.
hierarchy = add_quotes(
"/"
+ getattr(self, "hierarchy", ".").replace(".", "/")
+ "/"
+ str(randint(0, 2 ** 64 - 1))
)
tstamps = hierarchy
if tool is None:
tool = skidl.get_default_tool()
self.test_validity()
# Don't add anything to the XML if no pins are on this net.
if not self.get_pins():
return
try:
gen_func = getattr(self, "_gen_xml_net_{}".format(tool))
return gen_func()
except AttributeError:
log_and_raise(
logger,
ValueError,
"Can't generate XML in an unknown ECAD tool format ({}).".format(tool),
)