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How to use the dace.properties.CodeProperty.from_string function in dace

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github spcl / dace / tests / intel_fpga / gemm_systolic_array.py View on Github external
"B_stream_in", dace.float32, storage=dace.dtypes.StorageType.FPGA_Local)
    B_pipe_out = state.add_stream(
        "B_stream_out",
        dace.float32,
        storage=dace.dtypes.StorageType.FPGA_Local)

    # N-loop
    sdfg.add_edge(
        n_begin,
        n_entry,
        dace.graph.edges.InterstateEdge(assignments={"n0": 0}))
    sdfg.add_edge(
        n_entry,
        k_begin,
        dace.graph.edges.InterstateEdge(
            condition=dace.properties.CodeProperty.from_string(
                "n0 < N / P", language=dace.dtypes.Language.Python)))
    sdfg.add_edge(
        n_entry,
        n_end,
        dace.graph.edges.InterstateEdge(
            condition=dace.properties.CodeProperty.from_string(
                "n0 >= N / P", language=dace.dtypes.Language.Python)))

    # K-loop
    sdfg.add_edge(
        k_begin,
        k_entry,
        dace.graph.edges.InterstateEdge(assignments={"k": 0}))
    sdfg.add_edge(
        k_entry,
        a_begin,
github spcl / dace / samples / fpga / jacobi_fpga_stream.py View on Github external
sdfg.add_edge(y_end, time_entry,
                  dace.sdfg.InterstateEdge(assignments={"t": "t + 1"}))
    sdfg.add_edge(x_end, y_entry,
                  dace.sdfg.InterstateEdge(assignments={"y": "y + 1"}))
    sdfg.add_edge(loop_body, x_entry,
                  dace.sdfg.InterstateEdge(assignments={"x": "x + 1"}))

    sdfg.add_edge(
        time_entry, time_end,
        dace.sdfg.InterstateEdge(
            condition=dace.properties.CodeProperty.from_string(
                "t >= T", language=dace.dtypes.Language.Python)))
    sdfg.add_edge(
        y_entry, y_end,
        dace.sdfg.InterstateEdge(
            condition=dace.properties.CodeProperty.from_string(
                "y >= H", language=dace.dtypes.Language.Python)))
    sdfg.add_edge(
        x_entry, x_end,
        dace.sdfg.InterstateEdge(
            condition=dace.properties.CodeProperty.from_string(
                "x >= W", language=dace.dtypes.Language.Python)))

    mem_read = loop_body.add_array("mem_read", (2, H, W),
                                   dtype,
                                   storage=dace.dtypes.StorageType.FPGA_Global)
    stream_to_kernel = loop_body.add_stream(
        "stream_to_kernel",
        dtype,
        1,
        storage=dace.dtypes.StorageType.FPGA_Global)
github spcl / dace / samples / fpga / spmv_fpga_stream.py View on Github external
rows_entry, rows_end,
        InterstateEdge(condition=CodeProperty.from_string(
            "h >= H", language=Language.Python)))

    sdfg.add_edge(shift_rowptr, read_rowptr, InterstateEdge())
    sdfg.add_edge(read_rowptr, cols_begin, InterstateEdge())

    sdfg.add_edge(cols_begin, cols_entry,
                  InterstateEdge(assignments={"c": "0"}))
    sdfg.add_edge(
        cols_entry, body,
        InterstateEdge(condition=CodeProperty.from_string(
            "c < row_end - row_begin", language=Language.Python)))
    sdfg.add_edge(
        cols_entry, cols_end,
        InterstateEdge(condition=CodeProperty.from_string(
            "c >= row_end - row_begin", language=Language.Python)))

    sdfg.add_edge(body, cols_entry, InterstateEdge(assignments={"c": "c + 1"}))
    sdfg.add_edge(cols_end, post_state, InterstateEdge())
    sdfg.add_edge(post_state, rows_entry,
                  InterstateEdge(assignments={"h": "h + 1"}))

    row_end_first = pre_state.add_scalar("row_end",
                                         itype,
                                         transient=True,
                                         storage=StorageType.FPGA_Registers)
    row_pipe_first = pre_state.add_stream("row_pipe",
                                          itype,
                                          storage=StorageType.FPGA_Local)
    pre_state.add_memlet_path(row_pipe_first,
                              row_end_first,
github spcl / dace / samples / fpga / jacobi_fpga_stream.py View on Github external
dace.sdfg.InterstateEdge(assignments={"x": "x + 1"}))

    sdfg.add_edge(
        time_entry, time_end,
        dace.sdfg.InterstateEdge(
            condition=dace.properties.CodeProperty.from_string(
                "t >= T", language=dace.dtypes.Language.Python)))
    sdfg.add_edge(
        y_entry, y_end,
        dace.sdfg.InterstateEdge(
            condition=dace.properties.CodeProperty.from_string(
                "y >= H", language=dace.dtypes.Language.Python)))
    sdfg.add_edge(
        x_entry, x_end,
        dace.sdfg.InterstateEdge(
            condition=dace.properties.CodeProperty.from_string(
                "x >= W", language=dace.dtypes.Language.Python)))

    stream_in = pre_shift.add_stream(
        "stream_in", dtype, 1, storage=dace.dtypes.StorageType.FPGA_Global)
    stream_out = loop_body.add_stream(
        "stream_out", dtype, 1, storage=dace.dtypes.StorageType.FPGA_Global)

    rows_in = pre_shift.add_array("row_buffers", (2, W),
                                  dtype,
                                  transient=True,
                                  storage=dace.dtypes.StorageType.FPGA_Local,
                                  lifetime=dace.dtypes.AllocationLifetime.SDFG)
    rows_out = post_shift.add_array(
        "row_buffers", (2, W),
        dtype,
        transient=True,
github spcl / dace / samples / fpga / filter_fpga_vectorized.py View on Github external
src_conn="i_write_out",
                               memlet=Memlet.simple(i_write_zero, "0"))

    sdfg.add_edge(loop_begin, loop_entry,
                  dace.sdfg.InterstateEdge(assignments={"i": 0}))

    sdfg.add_edge(
        loop_entry, state,
        dace.sdfg.InterstateEdge(
            condition=dace.properties.CodeProperty.from_string(
                "i < N + W", language=dace.dtypes.Language.Python)))

    sdfg.add_edge(
        loop_entry, loop_end,
        dace.sdfg.InterstateEdge(
            condition=dace.properties.CodeProperty.from_string(
                "i >= N + W", language=dace.dtypes.Language.Python)))

    sdfg.add_edge(state, loop_entry,
                  dace.sdfg.InterstateEdge(assignments={"i": "i + W"}))

    B = state.add_array("B_mem", [N / W],
                        dtype=vtype,
                        storage=StorageType.FPGA_Global)
    B_pipe = state.add_stream("_B_pipe",
                              dtype=vtype,
                              buffer_size=buffer_size,
                              storage=StorageType.FPGA_Local)
    valid_pipe = state.add_stream("_valid_pipe",
                                  dtype=dace.dtypes.bool,
                                  buffer_size=buffer_size,
                                  storage=StorageType.FPGA_Local)
github spcl / dace / samples / fpga / jacobi_fpga_systolic.py View on Github external
sdfg.add_edge(time_begin, time_entry,
                  dace.sdfg.InterstateEdge(assignments={"t": 0}))
    sdfg.add_edge(y_begin, y_entry,
                  dace.sdfg.InterstateEdge(assignments={"y": 1}))
    sdfg.add_edge(x_begin, x_entry,
                  dace.sdfg.InterstateEdge(assignments={"x": 1}))

    sdfg.add_edge(
        time_entry, y_begin,
        dace.sdfg.InterstateEdge(
            condition=dace.properties.CodeProperty.from_string(
                "t < T / P", language=dace.dtypes.Language.Python)))
    sdfg.add_edge(
        y_entry, x_begin,
        dace.sdfg.InterstateEdge(
            condition=dace.properties.CodeProperty.from_string(
                "y < H - 1", language=dace.dtypes.Language.Python)))
    sdfg.add_edge(
        x_entry, loop_body,
        dace.sdfg.InterstateEdge(
            condition=dace.properties.CodeProperty.from_string(
                "x < W - 1", language=dace.dtypes.Language.Python)))

    sdfg.add_edge(y_end, time_entry,
                  dace.sdfg.InterstateEdge(assignments={"t": "t + 1"}))
    sdfg.add_edge(x_end, y_entry,
                  dace.sdfg.InterstateEdge(assignments={"y": "y + 1"}))
    sdfg.add_edge(loop_body, x_entry,
                  dace.sdfg.InterstateEdge(assignments={"x": "x + 1"}))

    sdfg.add_edge(
        time_entry, time_end,
github spcl / dace / samples / fpga / jacobi_fpga_systolic.py View on Github external
dace.sdfg.InterstateEdge(assignments={"x": "x + 1"}))

    sdfg.add_edge(
        time_entry, time_end,
        dace.sdfg.InterstateEdge(
            condition=dace.properties.CodeProperty.from_string(
                "t >= T / P", language=dace.dtypes.Language.Python)))
    sdfg.add_edge(
        y_entry, y_end,
        dace.sdfg.InterstateEdge(
            condition=dace.properties.CodeProperty.from_string(
                "y >= H", language=dace.dtypes.Language.Python)))
    sdfg.add_edge(
        x_entry, x_end,
        dace.sdfg.InterstateEdge(
            condition=dace.properties.CodeProperty.from_string(
                "x >= W", language=dace.dtypes.Language.Python)))

    mem_read = loop_body.add_array("mem_read", (2, H, W),
                                   dtype,
                                   storage=dace.dtypes.StorageType.FPGA_Global)
    pipe = loop_body.add_stream("pipe",
                                dtype,
                                1,
                                storage=dace.dtypes.StorageType.FPGA_Global)

    # Read from memory
    read_memory_memlet = dace.memlet.Memlet(
        mem_read,
        dace.symbolic.pystr_to_symbolic("1"),
        dace.properties.SubsetProperty.from_string("t%2, y, x"),
        1,
github spcl / dace / samples / fpga / gemm_fpga_stream.py View on Github external
nested_sdfg = dace.SDFG("gemm_nested")

    if_state_c = nested_sdfg.add_state("if_state_c")
    then_state_c = nested_sdfg.add_state("then_state_c")
    else_state_c = nested_sdfg.add_state("else_state_c")
    if_state_a = nested_sdfg.add_state("if_state_a")
    then_state_a = nested_sdfg.add_state("then_state_a")
    # No else state is necessary, but control flow detection seems to be broken
    # for ifs with no else branch
    else_state_a = nested_sdfg.add_state("else_state_a")
    compute_state = nested_sdfg.add_state("compute_state")
    nested_sdfg.add_edge(
        if_state_c, then_state_c,
        dace.sdfg.InterstateEdge(
            condition=dace.properties.CodeProperty.from_string(
                "k == 0", language=dace.dtypes.Language.Python)))
    nested_sdfg.add_edge(
        if_state_c, else_state_c,
        dace.sdfg.InterstateEdge(
            condition=dace.properties.CodeProperty.from_string(
                "k != 0", language=dace.dtypes.Language.Python)))
    nested_sdfg.add_edge(then_state_c, if_state_a, dace.sdfg.InterstateEdge())
    nested_sdfg.add_edge(else_state_c, if_state_a, dace.sdfg.InterstateEdge())
    nested_sdfg.add_edge(
        if_state_a, then_state_a,
        dace.sdfg.InterstateEdge(
            condition=dace.properties.CodeProperty.from_string(
                "m == 0", language=dace.dtypes.Language.Python)))
    nested_sdfg.add_edge(
        if_state_a, else_state_a,
        dace.sdfg.InterstateEdge(
github spcl / dace / samples / fpga / spmv_fpga_stream.py View on Github external
def make_write_sdfg():

    sdfg = SDFG("spmv_write")

    begin = sdfg.add_state("begin")
    entry = sdfg.add_state("entry")
    state = sdfg.add_state("body")
    end = sdfg.add_state("end")

    sdfg.add_edge(begin, entry, InterstateEdge(assignments={"h": "0"}))

    sdfg.add_edge(
        entry, state,
        InterstateEdge(condition=CodeProperty.from_string(
            "h < H", language=Language.Python)))

    sdfg.add_edge(
        entry, end,
        InterstateEdge(condition=CodeProperty.from_string(
            "h >= H", language=Language.Python)))

    sdfg.add_edge(state, entry, InterstateEdge(assignments={"h": "h + 1"}))

    result_to_write_in = state.add_stream("b_pipe",
                                          dtype,
                                          storage=StorageType.FPGA_Local)
    b = state.add_array("b_mem", (H, ), dtype, storage=StorageType.FPGA_Global)

    state.add_memlet_path(result_to_write_in, b, memlet=Memlet.simple(b, "h"))

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Data-Centric Parallel Programming Framework

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