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def _post_process_successors(self, simrun, successors):
"""
:return: A list of successors
:rtype: list
"""
if simrun.initial_state.thumb and isinstance(simrun, simuvex.SimIRSB):
pyvex.set_iropt_level(0) # FIXME: Should we recovery the iropt level late?
it_counter = 0
conc_temps = {}
can_produce_exits = set()
bb = self.project.factory.block(simrun.addr, thumb=True)
for stmt in bb.vex.statements:
if stmt.tag == 'Ist_IMark':
if it_counter > 0:
it_counter -= 1
can_produce_exits.add(stmt.addr)
elif stmt.tag == 'Ist_WrTmp':
val = stmt.data
if val.tag == 'Iex_Const':
conc_temps[stmt.tmp] = val.con.val
elif stmt.tag == 'Ist_Put':
if stmt.offset == self.project.arch.registers['itstate'][0]:
# deal with thumb mode in ARM, sending an odd address and an offset
# into the string
byte_offset = 0
if thumb:
byte_offset = 1
addr += 1
l.debug("Creating pyvex.IRSB of arch %s at 0x%x", self.arch.name, addr)
if self.use_cache:
cache_key = (buff, addr, max_size, num_inst, self.arch.vex_arch, byte_offset, thumb, opt_level)
if cache_key in self.irsb_cache:
return self.irsb_cache[cache_key]
pyvex.set_iropt_level(opt_level)
try:
if passed_max_size and not passed_num_inst:
block = SerializableIRSB(bytes=buff, mem_addr=addr, num_bytes=max_size, arch=self.arch, bytes_offset=byte_offset, traceflags=traceflags)
elif not passed_max_size and passed_num_inst:
block = SerializableIRSB(bytes=buff, mem_addr=addr, num_inst=num_inst, arch=self.arch, bytes_offset=byte_offset, traceflags=traceflags)
else:
block = SerializableIRSB(bytes=buff, mem_addr=addr, num_bytes=min(size, max_size), num_inst=num_inst, arch=self.arch, bytes_offset=byte_offset, traceflags=traceflags)
except pyvex.PyVEXError:
l.debug("VEX translation error at 0x%x", addr)
l.debug("Using bytes: " + str(pyvex.ffi.buffer(buff, size)).encode('hex'))
e_type, value, traceback = sys.exc_info()
raise AngrTranslationError, ("Translation error", e_type, value), traceback
if self.use_cache:
self.irsb_cache[cache_key] = block
def __init__(self,manager):
self._manager = manager
self._header = self._manager._header
self.fqueue = []
self.fqueue_sucess = []
self.fqueue_sucess_addr = []
self.new_fb_list = []
self.new_bb_list = []
pyvex.set_iropt_level(1)
def __init__(self,manager):
self._manager = manager
self._header = self._manager._header
self.fqueue = {}
self.fqueue_sucess = {}
self.new_fb_list = {}
self.new_bb_list = []
self.string_list = {}
pyvex.set_iropt_level(1)
buff, size = self._load_bytes(addr, max_size, state=backup_state)
if not buff or size == 0:
raise AngrMemoryError("No bytes in memory for block starting at %#x." % addr)
# deal with thumb mode in ARM, sending an odd address and an offset
# into the string
byte_offset = 0
real_addr = addr
if thumb:
byte_offset = 1
addr += 1
l.debug("Creating pyvex.IRSB of arch %s at %#x", arch.name, addr)
pyvex.set_iropt_level(opt_level)
try:
if passed_max_size and not passed_num_inst:
irsb = pyvex.IRSB(buff, addr, arch,
num_bytes=size,
bytes_offset=byte_offset,
traceflags=traceflags)
elif not passed_max_size and passed_num_inst:
irsb = pyvex.IRSB(buff, addr, arch,
num_bytes=VEX_IRSB_MAX_SIZE,
num_inst=num_inst,
bytes_offset=byte_offset,
traceflags=traceflags)
elif passed_max_size and passed_num_inst:
irsb = pyvex.IRSB(buff, addr, arch,
num_bytes=size,
num_inst=num_inst,