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:param stopbit: stop bit count
:param parity: parity mode as a single uppercase character
:param break_: force break event
"""
bytelength = {7: Ftdi.BITS_7,
8: Ftdi.BITS_8}
parities = {'N': Ftdi.PARITY_NONE,
'O': Ftdi.PARITY_ODD,
'E': Ftdi.PARITY_EVEN,
'M': Ftdi.PARITY_MARK,
'S': Ftdi.PARITY_SPACE}
stopbits = {1: Ftdi.STOP_BIT_1,
1.5: Ftdi.STOP_BIT_15,
2: Ftdi.STOP_BIT_2}
if parity not in parities:
raise FtdiFeatureError("Unsupported parity")
if bits not in bytelength:
raise FtdiFeatureError("Unsupported byte length")
if stopbit not in stopbits:
raise FtdiFeatureError("Unsupported stop bits")
value = bits & 0x0F
try:
value |= {Ftdi.PARITY_NONE: 0x00 << 8,
Ftdi.PARITY_ODD: 0x01 << 8,
Ftdi.PARITY_EVEN: 0x02 << 8,
Ftdi.PARITY_MARK: 0x03 << 8,
Ftdi.PARITY_SPACE: 0x04 << 8}[parities[parity]]
value |= {Ftdi.STOP_BIT_1: 0x00 << 11,
Ftdi.STOP_BIT_15: 0x01 << 11,
Ftdi.STOP_BIT_2: 0x02 << 11}[stopbits[stopbit]]
if break_ == Ftdi.BREAK_ON:
value |= 0x01 << 14
def _set_frequency(self, frequency: float) -> float:
"""Convert a frequency value into a TCK divisor setting"""
if not self.is_mpsse:
raise FtdiFeatureError('Cannot change frequency w/ current mode')
if frequency > self.frequency_max:
raise FtdiFeatureError('Unsupported frequency: %f' % frequency)
# Calculate base speed clock divider
divcode = Ftdi.ENABLE_CLK_DIV5
divisor = int((Ftdi.BUS_CLOCK_BASE+frequency/2)/frequency)-1
divisor = max(0, min(0xFFFF, divisor))
actual_freq = Ftdi.BUS_CLOCK_BASE/(divisor+1)
error = (actual_freq/frequency)-1
# Should we use high speed clock available in H series?
if self.is_H_series:
# Calculate high speed clock divider
divisor_hs = int((Ftdi.BUS_CLOCK_HIGH+frequency/2)/frequency)-1
divisor_hs = max(0, min(0xFFFF, divisor_hs))
actual_freq_hs = Ftdi.BUS_CLOCK_HIGH/(divisor_hs+1)
error_hs = (actual_freq_hs/frequency)-1
# Enable if closer to desired frequency (percentually)
if abs(error_hs) < abs(error):
divcode = Ftdi.DISABLE_CLK_DIV5
def _set_frequency(self, frequency: float) -> float:
"""Convert a frequency value into a TCK divisor setting"""
if not self.is_mpsse:
raise FtdiFeatureError('Cannot change frequency w/ current mode')
if frequency > self.frequency_max:
raise FtdiFeatureError('Unsupported frequency: %f' % frequency)
# Calculate base speed clock divider
divcode = Ftdi.ENABLE_CLK_DIV5
divisor = int((Ftdi.BUS_CLOCK_BASE+frequency/2)/frequency)-1
divisor = max(0, min(0xFFFF, divisor))
actual_freq = Ftdi.BUS_CLOCK_BASE/(divisor+1)
error = (actual_freq/frequency)-1
# Should we use high speed clock available in H series?
if self.is_H_series:
# Calculate high speed clock divider
divisor_hs = int((Ftdi.BUS_CLOCK_HIGH+frequency/2)/frequency)-1
divisor_hs = max(0, min(0xFFFF, divisor_hs))
actual_freq_hs = Ftdi.BUS_CLOCK_HIGH/(divisor_hs+1)
error_hs = (actual_freq_hs/frequency)-1
# Enable if closer to desired frequency (percentually)
kwargs['initial'] = self.IDLE | (io_out & self._gpio_mask)
kwargs['frequency'] = (3.0*frequency)/2.0
if not isinstance(url, str):
frequency = self._ftdi.open_mpsse_from_device(
url, interface=interface, **kwargs)
else:
frequency = self._ftdi.open_mpsse_from_url(url, **kwargs)
self._frequency = (2.0*frequency)/3.0
self._tx_size, self._rx_size = self._ftdi.fifo_sizes
self._ftdi.enable_adaptive_clock(clkstrch)
self._ftdi.enable_3phase_clock(True)
try:
self._ftdi.enable_drivezero_mode(self.SCL_BIT |
self.SDA_O_BIT |
self.SDA_I_BIT)
except FtdiFeatureError:
# when open collector feature is not available (FT2232, FT4232)
# SDA line is temporary move to high-z to enable ACK/NACK
# read back from slave
self._fake_tristate = True
self._wide_port = self._ftdi.has_wide_port
if not self._wide_port:
self._set_gpio_direction(8, io_out & 0xFF, io_dir & 0xFF)
def fifo_sizes(self) -> Tuple[int, int]:
"""Return the (TX, RX) tupple of hardware FIFO sizes
:return: 2-tuple of TX, RX FIFO size in bytes
"""
try:
return Ftdi.FIFO_SIZES[self.device_version]
except KeyError:
raise FtdiFeatureError('Unsupported device: 0x%04x' %
self.device_version)
bytelength = {7: Ftdi.BITS_7,
8: Ftdi.BITS_8}
parities = {'N': Ftdi.PARITY_NONE,
'O': Ftdi.PARITY_ODD,
'E': Ftdi.PARITY_EVEN,
'M': Ftdi.PARITY_MARK,
'S': Ftdi.PARITY_SPACE}
stopbits = {1: Ftdi.STOP_BIT_1,
1.5: Ftdi.STOP_BIT_15,
2: Ftdi.STOP_BIT_2}
if parity not in parities:
raise FtdiFeatureError("Unsupported parity")
if bits not in bytelength:
raise FtdiFeatureError("Unsupported byte length")
if stopbit not in stopbits:
raise FtdiFeatureError("Unsupported stop bits")
value = bits & 0x0F
try:
value |= {Ftdi.PARITY_NONE: 0x00 << 8,
Ftdi.PARITY_ODD: 0x01 << 8,
Ftdi.PARITY_EVEN: 0x02 << 8,
Ftdi.PARITY_MARK: 0x03 << 8,
Ftdi.PARITY_SPACE: 0x04 << 8}[parities[parity]]
value |= {Ftdi.STOP_BIT_1: 0x00 << 11,
Ftdi.STOP_BIT_15: 0x01 << 11,
Ftdi.STOP_BIT_2: 0x02 << 11}[stopbits[stopbit]]
if break_ == Ftdi.BREAK_ON:
value |= 0x01 << 14
except KeyError:
raise ValueError('Invalid line property')
if self._ctrl_transfer_out(Ftdi.SIO_REQ_SET_DATA, value):
raise FtdiError('Unable to set line property')