How to use the cocotb.clock.Clock function in cocotb

def simple_wb_test(dut):
    cocotb.fork(Clock(dut.wb_clk_i, 1000).start())

    for i in range(100):
        yield RisingEdge(dut.wb_clk_i)

def test_readwrite_in_readonly(dut):
    """Test doing invalid sim operation"""
    global exited
    exited = False
    clk_gen = cocotb.fork(Clock(dut.clk, 100).start())
    coro = cocotb.fork(do_test_readwrite_in_readonly(dut))
    yield [Join(coro), Timer(10000)]
    clk_gen.kill()
    if exited is not True:
        raise TestFailure

async def test_ndim_array_indexes(dut):
    """Test getting and setting values of multi-dimensional array indexes."""

    cocotb.fork(Clock(dut.clk, 1000, 'ns').start())

    dut.array_2d <= [
        [0xF0, 0xE0, 0xD0, 0xC0],
        [0xB0, 0xA0, 0x90, 0x80]
    ]

    await Timer(1000, 'ns')

    # Check indices
    _check_value(tlog, dut.array_2d[1]    , [0xB0, 0xA0, 0x90, 0x80])
    _check_value(tlog, dut.array_2d[0][31], 0xF0)
    _check_value(tlog, dut.array_2d[1][29], 0x90)
    _check_value(tlog, dut.array_2d[1][28], 0x80)

    # Get sub-handles through NonHierarchyIndexableObject.__getitem__
    dut.array_2d[1]     <= [0xDE, 0xAD, 0xBE, 0xEF]

def issue_120_scheduling(dut):

    cocotb.fork(Clock(dut.clk, 2500).start())
    cocotb.fork(monitor(dut))
    yield RisingEdge(dut.clk)

    # First attempt, not from coroutine - works as expected
    for i in range(2):
        dut.stream_in_valid = 1
        yield RisingEdge(dut.clk)
        dut.stream_in_valid = 0

    yield RisingEdge(dut.clk)

    # Failure - we don't drive valid on the rising edge even though
    # behaviour should be identical to the above
    yield send_data(dut)
    dut.stream_in_valid = 1
    yield RisingEdge(dut.clk)

def test_afterdelay_in_readonly(dut):
    """Test doing invalid sim operation"""
    global exited
    exited = False
    clk_gen = cocotb.fork(Clock(dut.clk, 100).start())
    coro = cocotb.fork(do_test_afterdelay_in_readonly(dut, 0))
    yield [Join(coro), Timer(1000)]
    clk_gen.kill()
    if exited is not True:
        raise TestFailure

def __init__(self, dut, avlproperties={}):
        self.dut = dut
        # Launch clock
        dut.reset = 1
        clk_gen = cocotb.fork(Clock(dut.clk, 10).start())

        # Bytes aligned memory
        self.memdict = {value: value for value in range(0x1000)}

        self.avl32 = AvalonMemory(dut, "master", dut.clk,
                                  memory=self.memdict,
                                  readlatency_min=0,
                                  avl_properties=avlproperties)

def test_fork_and_monitor(dut, period=1000, clocks=6):
    cocotb.fork(Clock(dut.clk, period).start())

    # Ensure the clock has started
    yield RisingEdge(dut.clk)

    timer = Timer(period + 10)
    task = cocotb.fork(count_edges_cycles(dut.clk, clocks))
    count = 0
    expect = clocks - 1

    while True:
        result = yield [timer, task.join()]
        if count > expect:
            raise TestFailure("Task didn't complete in expected time")
        if result is timer:
            dut._log.info("Count %d: Task still running" % count)
            count += 1

def test_coroutine_close_down(dut):
    clk_gen = cocotb.fork(Clock(dut.clk, 100).start())

    coro_one = cocotb.fork(clock_one(dut))
    coro_two = cocotb.fork(clock_two(dut))

    yield Join(coro_one)
    yield Join(coro_two)

    dut._log.info("Back from joins")

def test_direct_signal_indexing(dut):
    """Test directly accessing signal/net data in arrays, i.e. not iterating"""

    tlog = logging.getLogger("cocotb.test")

    cocotb.fork(Clock(dut.clk, 1000).start())

    dut.port_desc_in <= 0
    dut.port_asc_in  <= 0
    dut.port_ofst_in <= 0

    yield Timer(2000)

    dut.port_desc_in[2] <= 1
    dut.port_asc_in[2]  <= 1
    dut.port_ofst_in[2] <= 1

    yield Timer(2000)

    tlog.info("Checking bit mapping from input to generate loops.")
    if int(dut.desc_gen[2].sig) != 1:
        raise TestFailure("Expected {0!r} to be a 1 but got {1}".format(dut.desc_gen[2].sig, int(dut.desc_gen[2].sig)))

def test_tree(dut):
    """Testing APBI2C core"""
    
    log = cocotb.logging.getLogger("cocotb.test")
    cocotb.fork(Clock(dut.PCLK, 1000).start())

    #instantiate the APB agent (monitor and driver) (see apb.py)
    apb = APBSlave(dut, name=None, clock=dut.PCLK)
    
    #instantiate the I2C monitor and driver (see i2c.py)
    i2c_monitor = I2CMonitor(dut, name="", clock=dut.PCLK)
    i2c_driver = I2CDriver(dut, name=None, clock=dut.PCLK)
            
    #write to config register via APB
    @cocotb.coroutine
    def config_write(addr, data):
        xaction = APBTransaction(addr, data, write=True)
        xaction.randomize()
        yield apb.send(xaction)
            
    #store observed I2C transactions